board/freescale/mpc8540ads/mpc8540ads.c

   1  /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003, Motorola Inc.
   4  * Xianghua Xiao, (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27
  28 #include <common.h>
  29 #include <pci.h>
  30 #include <asm/processor.h>
  31 #include <asm/immap_85xx.h>
  32 #include <spd.h>
  33 #include <libfdt.h>
  34 #include <fdt_support.h>
  35
  36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  37 extern void ddr_enable_ecc(unsigned int dram_size);
  38 #endif
  39
  40 extern long int spd_sdram(void);
  41
  42 void local_bus_init(void);
  43 void sdram_init(void);
  44 long int fixed_sdram(void);
  45
  46
  47 int board_early_init_f (void)
  48 {
  49     return 0;
  50 }
  51
  52 int checkboard (void)
  53 {
  54         puts("Board: ADS\n");
  55
  56 #ifdef CONFIG_PCI
  57         printf("    PCI1: 32 bit, %d MHz (compiled)\n",
  58                CONFIG_SYS_CLK_FREQ / 1000000);
  59 #else
  60         printf("    PCI1: disabled\n");
  61 #endif
  62
  63         /*
  64          * Initialize local bus.
  65          */
  66         local_bus_init();
  67
  68         return 0;
  69 }
  70
  71
  72 long int
  73 initdram(int board_type)
  74 {
  75         long dram_size = 0;
  76         extern long spd_sdram (void);
  77
  78         puts("Initializing\n");
  79
  80 #if defined(CONFIG_DDR_DLL)
  81         {
  82             volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  83             uint temp_ddrdll = 0;
  84
  85             /*
  86              * Work around to stabilize DDR DLL
  87              */
  88             temp_ddrdll = gur->ddrdllcr;
  89             gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
  90             asm("sync;isync;msync");
  91         }
  92 #endif
  93
  94 #if defined(CONFIG_SPD_EEPROM)
  95         dram_size = spd_sdram ();
  96 #else
  97         dram_size = fixed_sdram ();
  98 #endif
  99
 100 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 101         /*
 102          * Initialize and enable DDR ECC.
 103          */
 104         ddr_enable_ecc(dram_size);
 105 #endif
 106
 107         /*
 108          * Initialize SDRAM.
 109          */
 110         sdram_init();
 111
 112         puts("    DDR: ");
 113         return dram_size;
 114 }
 115
 116
 117 /*
 118  * Initialize Local Bus
 119  */
 120
 121 void
 122 local_bus_init(void)
 123 {
 124         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 125         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 126
 127         uint clkdiv;
 128         uint lbc_hz;
 129         sys_info_t sysinfo;
 130
 131         /*
 132          * Errata LBC11.
 133          * Fix Local Bus clock glitch when DLL is enabled.
 134          *
 135          * If localbus freq is < 66Mhz, DLL bypass mode must be used.
 136          * If localbus freq is > 133Mhz, DLL can be safely enabled.
 137          * Between 66 and 133, the DLL is enabled with an override workaround.
 138          */
 139
 140         get_sys_info(&sysinfo);
 141         clkdiv = lbc->lcrr & 0x0f;
 142         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 143
 144         if (lbc_hz < 66) {
 145                 lbc->lcrr = CFG_LBC_LCRR | 0x80000000;  /* DLL Bypass */
 146
 147         } else if (lbc_hz >= 133) {
 148                 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 149
 150         } else {
 151                 /*
 152                  * On REV1 boards, need to change CLKDIV before enable DLL.
 153                  * Default CLKDIV is 8, change it to 4 temporarily.
 154                  */
 155                 uint pvr = get_pvr();
 156                 uint temp_lbcdll = 0;
 157
 158                 if (pvr == PVR_85xx_REV1) {
 159                         /* FIXME: Justify the high bit here. */
 160                         lbc->lcrr = 0x10000004;
 161                 }
 162
 163                 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 164                 udelay(200);
 165
 166                 /*
 167                  * Sample LBC DLL ctrl reg, upshift it to set the
 168                  * override bits.
 169                  */
 170                 temp_lbcdll = gur->lbcdllcr;
 171                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 172                 asm("sync;isync;msync");
 173         }
 174 }
 175
 176
 177 /*
 178  * Initialize SDRAM memory on the Local Bus.
 179  */
 180
 181 void
 182 sdram_init(void)
 183 {
 184         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 185         uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 186
 187         puts("    SDRAM: ");
 188         print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 189
 190         /*
 191          * Setup SDRAM Base and Option Registers
 192          */
 193         lbc->or2 = CFG_OR2_PRELIM;
 194         lbc->br2 = CFG_BR2_PRELIM;
 195         lbc->lbcr = CFG_LBC_LBCR;
 196         asm("msync");
 197
 198         lbc->lsrt = CFG_LBC_LSRT;
 199         lbc->mrtpr = CFG_LBC_MRTPR;
 200         asm("sync");
 201
 202         /*
 203          * Configure the SDRAM controller.
 204          */
 205         lbc->lsdmr = CFG_LBC_LSDMR_1;
 206         asm("sync");
 207         *sdram_addr = 0xff;
 208         ppcDcbf((unsigned long) sdram_addr);
 209         udelay(100);
 210
 211         lbc->lsdmr = CFG_LBC_LSDMR_2;
 212         asm("sync");
 213         *sdram_addr = 0xff;
 214         ppcDcbf((unsigned long) sdram_addr);
 215         udelay(100);
 216
 217         lbc->lsdmr = CFG_LBC_LSDMR_3;
 218         asm("sync");
 219         *sdram_addr = 0xff;
 220         ppcDcbf((unsigned long) sdram_addr);
 221         udelay(100);
 222
 223         lbc->lsdmr = CFG_LBC_LSDMR_4;
 224         asm("sync");
 225         *sdram_addr = 0xff;
 226         ppcDcbf((unsigned long) sdram_addr);
 227         udelay(100);
 228
 229         lbc->lsdmr = CFG_LBC_LSDMR_5;
 230         asm("sync");
 231         *sdram_addr = 0xff;
 232         ppcDcbf((unsigned long) sdram_addr);
 233         udelay(100);
 234 }
 235
 236
 237 #if defined(CFG_DRAM_TEST)
 238 int testdram (void)
 239 {
 240         uint *pstart = (uint *) CFG_MEMTEST_START;
 241         uint *pend = (uint *) CFG_MEMTEST_END;
 242         uint *p;
 243
 244         printf("SDRAM test phase 1:\n");
 245         for (p = pstart; p < pend; p++)
 246                 *p = 0xaaaaaaaa;
 247
 248         for (p = pstart; p < pend; p++) {
 249                 if (*p != 0xaaaaaaaa) {
 250                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 251                         return 1;
 252                 }
 253         }
 254
 255         printf("SDRAM test phase 2:\n");
 256         for (p = pstart; p < pend; p++)
 257                 *p = 0x55555555;
 258
 259         for (p = pstart; p < pend; p++) {
 260                 if (*p != 0x55555555) {
 261                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 262                         return 1;
 263                 }
 264         }
 265
 266         printf("SDRAM test passed.\n");
 267         return 0;
 268 }
 269 #endif
 270
 271
 272 #if !defined(CONFIG_SPD_EEPROM)
 273 /*************************************************************************
 274  *  fixed sdram init -- doesn't use serial presence detect.
 275  ************************************************************************/
 276 long int fixed_sdram (void)
 277 {
 278   #ifndef CFG_RAMBOOT
 279         volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 280
 281         ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 282         ddr->cs0_config = CFG_DDR_CS0_CONFIG;
 283         ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 284         ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
 285         ddr->sdram_mode = CFG_DDR_MODE;
 286         ddr->sdram_interval = CFG_DDR_INTERVAL;
 287     #if defined (CONFIG_DDR_ECC)
 288         ddr->err_disable = 0x0000000D;
 289         ddr->err_sbe = 0x00ff0000;
 290     #endif
 291         asm("sync;isync;msync");
 292         udelay(500);
 293     #if defined (CONFIG_DDR_ECC)
 294         /* Enable ECC checking */
 295         ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
 296     #else
 297         ddr->sdram_cfg = CFG_DDR_CONTROL;
 298     #endif
 299         asm("sync; isync; msync");
 300         udelay(500);
 301   #endif
 302         return CFG_SDRAM_SIZE * 1024 * 1024;
 303 }
 304 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 305
 306
 307 #if defined(CONFIG_PCI)
 308 /*
 309  * Initialize PCI Devices, report devices found.
 310  */
 311
 312
 313 static struct pci_controller hose;
 314
 315 #endif  /* CONFIG_PCI */
 316
 317
 318 void
 319 pci_init_board(void)
 320 {
 321 #ifdef CONFIG_PCI
 322         pci_mpc85xx_init(&hose);
 323 #endif /* CONFIG_PCI */
 324 }
 325
 326
 327 #if defined(CONFIG_OF_BOARD_SETUP)
 328 void
 329 ft_board_setup(void *blob, bd_t *bd)
 330 {
 331         int node, tmp[2];
 332         const char *path;
 333
 334         ft_cpu_setup(blob, bd);
 335
 336         node = fdt_path_offset(blob, "/aliases");
 337         tmp[0] = 0;
 338         if (node >= 0) {
 339 #ifdef CONFIG_PCI
 340                 path = fdt_getprop(blob, node, "pci0", NULL);
 341                 if (path) {
 342                         tmp[1] = hose.last_busno - hose.first_busno;
 343                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 344                 }
 345 #endif
 346         }
 347 }
 348 #endif