board/freescale/mpc8541cds/mpc8541cds.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  *
   4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <pci.h>
  27 #include <asm/processor.h>
  28 #include <asm/mmu.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_ddr_sdram.h>
  31 #include <ioports.h>
  32 #include <spd_sdram.h>
  33 #include <libfdt.h>
  34 #include <fdt_support.h>
  35
  36 #include "../common/cadmus.h"
  37 #include "../common/eeprom.h"
  38 #include "../common/via.h"
  39
  40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  41 extern void ddr_enable_ecc(unsigned int dram_size);
  42 #endif
  43
  44 void local_bus_init(void);
  45 void sdram_init(void);
  46
  47 /*
  48  * I/O Port configuration table
  49  *
  50  * if conf is 1, then that port pin will be configured at boot time
  51  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  52  */
  53
  54 const iop_conf_t iop_conf_tab[4][32] = {
  55
  56     /* Port A configuration */
  57     {   /*            conf ppar psor pdir podr pdat */
  58         /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
  59         /* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
  60         /* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
  61         /* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
  62         /* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
  63         /* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
  64         /* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
  65         /* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
  66         /* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
  67         /* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
  68         /* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
  69         /* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
  70         /* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
  71         /* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
  72         /* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
  73         /* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
  74         /* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
  75         /* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
  76         /* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
  77         /* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
  78         /* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
  79         /* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
  80         /* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
  81         /* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
  82         /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  83         /* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
  84         /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  85         /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  86         /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  87         /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  88         /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
  89         /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  90     },
  91
  92     /* Port B configuration */
  93     {   /*            conf ppar psor pdir podr pdat */
  94         /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  95         /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  96         /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  97         /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  98         /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  99         /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
 100         /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
 101         /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
 102         /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
 103         /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
 104         /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
 105         /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 106         /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 107         /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
 108         /* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
 109         /* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
 110         /* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
 111         /* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
 112         /* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
 113         /* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
 114         /* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 115         /* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 116         /* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 117         /* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 118         /* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 119         /* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 120         /* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 121         /* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 122         /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 123         /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 124         /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 125         /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 126     },
 127
 128     /* Port C */
 129     {   /*            conf ppar psor pdir podr pdat */
 130         /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 131         /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 132         /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
 133         /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 134         /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
 135         /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 136         /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 137         /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 138         /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
 139         /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
 140         /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 141         /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 142         /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
 143         /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
 144         /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 145         /* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
 146         /* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
 147         /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 148         /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 149         /* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 150         /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
 151         /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
 152         /* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
 153         /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 154         /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 155         /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 156         /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 157         /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 158         /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 159         /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 160         /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 161         /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 162     },
 163
 164     /* Port D */
 165     {   /*            conf ppar psor pdir podr pdat */
 166         /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 167         /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 168         /* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
 169         /* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
 170         /* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
 171         /* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
 172         /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 173         /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 174         /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 175         /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 176         /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 177         /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 178         /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 179         /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 180         /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 181         /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
 182         /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 183         /* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
 184         /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 185         /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 186         /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 187         /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 188         /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 189         /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 190         /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 191         /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 192         /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 193         /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 194         /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 195         /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 196         /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 197         /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 198     }
 199 };
 200
 201 int checkboard (void)
 202 {
 203         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 204
 205         /* PCI slot in USER bits CSR[6:7] by convention. */
 206         uint pci_slot = get_pci_slot ();
 207
 208         uint pci_dual = get_pci_dual ();        /* PCI DUAL in CM_PCI[3] */
 209         uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
 210         uint pci1_clk_sel = gur->porpllsr & 0x8000;     /* PORPLLSR[16] */
 211         uint pci2_clk_sel = gur->porpllsr & 0x4000;     /* PORPLLSR[17] */
 212
 213         uint pci1_speed = get_clock_freq ();    /* PCI PSPEED in [4:5] */
 214
 215         uint cpu_board_rev = get_cpu_board_revision ();
 216
 217         printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
 218                 get_board_version (), pci_slot);
 219
 220         printf ("CPU Board Revision %d.%d (0x%04x)\n",
 221                 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
 222                 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
 223
 224         printf ("    PCI1: %d bit, %s MHz, %s\n",
 225                 (pci1_32) ? 32 : 64,
 226                 (pci1_speed == 33000000) ? "33" :
 227                 (pci1_speed == 66000000) ? "66" : "unknown",
 228                 pci1_clk_sel ? "sync" : "async");
 229
 230         if (pci_dual) {
 231                 printf ("    PCI2: 32 bit, 66 MHz, %s\n",
 232                         pci2_clk_sel ? "sync" : "async");
 233         } else {
 234                 printf ("    PCI2: disabled\n");
 235         }
 236
 237         /*
 238          * Initialize local bus.
 239          */
 240         local_bus_init ();
 241
 242         return 0;
 243 }
 244
 245 phys_size_t
 246 initdram(int board_type)
 247 {
 248         long dram_size = 0;
 249
 250         puts("Initializing\n");
 251
 252 #if defined(CONFIG_DDR_DLL)
 253         {
 254                 /*
 255                  * Work around to stabilize DDR DLL MSYNC_IN.
 256                  * Errata DDR9 seems to have been fixed.
 257                  * This is now the workaround for Errata DDR11:
 258                  *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 259                  */
 260
 261                 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 262
 263                 gur->ddrdllcr = 0x81000000;
 264                 asm("sync;isync;msync");
 265                 udelay(200);
 266         }
 267 #endif
 268         dram_size = fsl_ddr_sdram();
 269         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 270         dram_size *= 0x100000;
 271
 272 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 273         /*
 274          * Initialize and enable DDR ECC.
 275          */
 276         ddr_enable_ecc(dram_size);
 277 #endif
 278         /*
 279          * SDRAM Initialization
 280          */
 281         sdram_init();
 282
 283         puts("    DDR: ");
 284         return dram_size;
 285 }
 286
 287 /*
 288  * Initialize Local Bus
 289  */
 290 void
 291 local_bus_init(void)
 292 {
 293         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 294         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 295
 296         uint clkdiv;
 297         uint lbc_hz;
 298         sys_info_t sysinfo;
 299         uint temp_lbcdll;
 300
 301         /*
 302          * Errata LBC11.
 303          * Fix Local Bus clock glitch when DLL is enabled.
 304          *
 305          * If localbus freq is < 66Mhz, DLL bypass mode must be used.
 306          * If localbus freq is > 133Mhz, DLL can be safely enabled.
 307          * Between 66 and 133, the DLL is enabled with an override workaround.
 308          */
 309
 310         get_sys_info(&sysinfo);
 311         clkdiv = lbc->lcrr & 0x0f;
 312         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 313
 314         if (lbc_hz < 66) {
 315                 lbc->lcrr |= 0x80000000;        /* DLL Bypass */
 316
 317         } else if (lbc_hz >= 133) {
 318                 lbc->lcrr &= (~0x80000000);             /* DLL Enabled */
 319
 320         } else {
 321                 lbc->lcrr &= (~0x8000000);      /* DLL Enabled */
 322                 udelay(200);
 323
 324                 /*
 325                  * Sample LBC DLL ctrl reg, upshift it to set the
 326                  * override bits.
 327                  */
 328                 temp_lbcdll = gur->lbcdllcr;
 329                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 330                 asm("sync;isync;msync");
 331         }
 332 }
 333
 334 /*
 335  * Initialize SDRAM memory on the Local Bus.
 336  */
 337 void
 338 sdram_init(void)
 339 {
 340 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 341
 342         uint idx;
 343         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 344         uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 345         uint cpu_board_rev;
 346         uint lsdmr_common;
 347
 348         puts("    SDRAM: ");
 349
 350         print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 351
 352         /*
 353          * Setup SDRAM Base and Option Registers
 354          */
 355         lbc->or2 = CFG_OR2_PRELIM;
 356         asm("msync");
 357
 358         lbc->br2 = CFG_BR2_PRELIM;
 359         asm("msync");
 360
 361         lbc->lbcr = CFG_LBC_LBCR;
 362         asm("msync");
 363
 364
 365         lbc->lsrt = CFG_LBC_LSRT;
 366         lbc->mrtpr = CFG_LBC_MRTPR;
 367         asm("msync");
 368
 369         /*
 370          * Determine which address lines to use baed on CPU board rev.
 371          */
 372         cpu_board_rev = get_cpu_board_revision();
 373         lsdmr_common = CFG_LBC_LSDMR_COMMON;
 374         if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
 375                 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
 376         } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
 377                 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
 378         } else {
 379                 /*
 380                  * Assume something unable to identify itself is
 381                  * really old, and likely has lines 16/17 mapped.
 382                  */
 383                 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
 384         }
 385
 386         /*
 387          * Issue PRECHARGE ALL command.
 388          */
 389         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
 390         asm("sync;msync");
 391         *sdram_addr = 0xff;
 392         ppcDcbf((unsigned long) sdram_addr);
 393         udelay(100);
 394
 395         /*
 396          * Issue 8 AUTO REFRESH commands.
 397          */
 398         for (idx = 0; idx < 8; idx++) {
 399                 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
 400                 asm("sync;msync");
 401                 *sdram_addr = 0xff;
 402                 ppcDcbf((unsigned long) sdram_addr);
 403                 udelay(100);
 404         }
 405
 406         /*
 407          * Issue 8 MODE-set command.
 408          */
 409         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
 410         asm("sync;msync");
 411         *sdram_addr = 0xff;
 412         ppcDcbf((unsigned long) sdram_addr);
 413         udelay(100);
 414
 415         /*
 416          * Issue NORMAL OP command.
 417          */
 418         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
 419         asm("sync;msync");
 420         *sdram_addr = 0xff;
 421         ppcDcbf((unsigned long) sdram_addr);
 422         udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 423
 424 #endif  /* enable SDRAM init */
 425 }
 426
 427 #if defined(CONFIG_PCI)
 428 /* For some reason the Tundra PCI bridge shows up on itself as a
 429  * different device.  Work around that by refusing to configure it.
 430  */
 431 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
 432
 433 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 434         {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
 435         {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
 436         {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
 437                 mpc85xx_config_via_usbide, {0,0,0}},
 438         {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
 439                 mpc85xx_config_via_usb, {0,0,0}},
 440         {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
 441                 mpc85xx_config_via_usb2, {0,0,0}},
 442         {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
 443                 mpc85xx_config_via_power, {0,0,0}},
 444         {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
 445                 mpc85xx_config_via_ac97, {0,0,0}},
 446         {},
 447 };
 448
 449 static struct pci_controller hose[] = {
 450         { config_table: pci_mpc85xxcds_config_table,},
 451 #ifdef CONFIG_MPC85XX_PCI2
 452         {},
 453 #endif
 454 };
 455
 456 #endif  /* CONFIG_PCI */
 457
 458 void
 459 pci_init_board(void)
 460 {
 461 #ifdef CONFIG_PCI
 462         pci_mpc85xx_init(hose);
 463 #endif
 464 }
 465
 466 #if defined(CONFIG_OF_BOARD_SETUP)
 467 void
 468 ft_pci_setup(void *blob, bd_t *bd)
 469 {
 470         int node, tmp[2];
 471         const char *path;
 472
 473         node = fdt_path_offset(blob, "/aliases");
 474         tmp[0] = 0;
 475         if (node >= 0) {
 476 #ifdef CONFIG_PCI1
 477                 path = fdt_getprop(blob, node, "pci0", NULL);
 478                 if (path) {
 479                         tmp[1] = hose[0].last_busno - hose[0].first_busno;
 480                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 481                 }
 482 #endif
 483 #ifdef CONFIG_MPC85XX_PCI2
 484                 path = fdt_getprop(blob, node, "pci1", NULL);
 485                 if (path) {
 486                         tmp[1] = hose[1].last_busno - hose[1].first_busno;
 487                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 488                 }
 489 #endif
 490         }
 491 }
 492 #endif