board/freescale/mpc8544ds/mpc8544ds.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/fsl_pci.h>
  30 #include <asm/fsl_ddr_sdram.h>
  31 #include <asm/io.h>
  32 #include <miiphy.h>
  33 #include <libfdt.h>
  34 #include <fdt_support.h>
  35 #include <tsec.h>
  36 #include <netdev.h>
  37
  38 #include "../common/pixis.h"
  39 #include "../common/sgmii_riser.h"
  40
  41 int checkboard (void)
  42 {
  43         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  44         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  45         volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  46         u8 vboot;
  47         u8 *pixis_base = (u8 *)PIXIS_BASE;
  48
  49         if ((uint)&gur->porpllsr != 0xe00e0000) {
  50                 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
  51         }
  52         printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
  53                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  54                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  55                 in_8(pixis_base + PIXIS_PVER));
  56
  57         vboot = in_8(pixis_base + PIXIS_VBOOT);
  58         if (vboot & PIXIS_VBOOT_FMAP)
  59                 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
  60         else
  61                 puts ("Promjet\n");
  62
  63         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  64         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  65         ecm->eedr = 0xffffffff;         /* Clear ecm errors */
  66         ecm->eeer = 0xffffffff;         /* Enable ecm errors */
  67
  68         return 0;
  69 }
  70
  71 phys_size_t
  72 initdram(int board_type)
  73 {
  74         long dram_size = 0;
  75
  76         puts("Initializing\n");
  77
  78         dram_size = fsl_ddr_sdram();
  79
  80         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  81
  82         dram_size *= 0x100000;
  83
  84         puts("    DDR: ");
  85         return dram_size;
  86 }
  87
  88 #ifdef CONFIG_PCI1
  89 static struct pci_controller pci1_hose;
  90 #endif
  91
  92 #ifdef CONFIG_PCIE1
  93 static struct pci_controller pcie1_hose;
  94 #endif
  95
  96 #ifdef CONFIG_PCIE2
  97 static struct pci_controller pcie2_hose;
  98 #endif
  99
 100 #ifdef CONFIG_PCIE3
 101 static struct pci_controller pcie3_hose;
 102 #endif
 103
 104 int first_free_busno=0;
 105
 106 void
 107 pci_init_board(void)
 108 {
 109         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 110         uint devdisr = gur->devdisr;
 111         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 112         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 113
 114         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 115                 devdisr, io_sel, host_agent);
 116
 117         if (io_sel & 1) {
 118                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 119                         printf ("    eTSEC1 is in sgmii mode.\n");
 120                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 121                         printf ("    eTSEC3 is in sgmii mode.\n");
 122         }
 123
 124 #ifdef CONFIG_PCIE3
 125 {
 126         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 127         struct pci_controller *hose = &pcie3_hose;
 128         int pcie_ep = (host_agent == 1);
 129         int pcie_configured  = io_sel >= 6;
 130         struct pci_region *r = hose->regions;
 131
 132         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 133                 printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 134                         pcie_ep ? "End Point" : "Root Complex",
 135                         (uint)pci);
 136                 if (pci->pme_msg_det) {
 137                         pci->pme_msg_det = 0xffffffff;
 138                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 139                 }
 140                 printf ("\n");
 141
 142                 /* inbound */
 143                 r += fsl_pci_setup_inbound_windows(r);
 144
 145                 /* outbound memory */
 146                 pci_set_region(r++,
 147                                CONFIG_SYS_PCIE3_MEM_BUS,
 148                                CONFIG_SYS_PCIE3_MEM_PHYS,
 149                                CONFIG_SYS_PCIE3_MEM_SIZE,
 150                                PCI_REGION_MEM);
 151
 152                 /* outbound io */
 153                 pci_set_region(r++,
 154                                CONFIG_SYS_PCIE3_IO_BUS,
 155                                CONFIG_SYS_PCIE3_IO_PHYS,
 156                                CONFIG_SYS_PCIE3_IO_SIZE,
 157                                PCI_REGION_IO);
 158
 159 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
 160                 /* outbound memory */
 161                 pci_set_region(r++,
 162                                CONFIG_SYS_PCIE3_MEM_BUS2,
 163                                CONFIG_SYS_PCIE3_MEM_PHYS2,
 164                                CONFIG_SYS_PCIE3_MEM_SIZE2,
 165                                PCI_REGION_MEM);
 166 #endif
 167                 hose->region_count = r - hose->regions;
 168                 hose->first_busno=first_free_busno;
 169
 170                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 171
 172                 first_free_busno=hose->last_busno+1;
 173                 printf ("    PCIE3 on bus %02x - %02x\n",
 174                         hose->first_busno,hose->last_busno);
 175
 176                 /*
 177                  * Activate ULI1575 legacy chip by performing a fake
 178                  * memory access.  Needed to make ULI RTC work.
 179                  */
 180                 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
 181         } else {
 182                 printf ("    PCIE3: disabled\n");
 183         }
 184
 185  }
 186 #else
 187         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 188 #endif
 189
 190 #ifdef CONFIG_PCIE1
 191  {
 192         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 193         struct pci_controller *hose = &pcie1_hose;
 194         int pcie_ep = (host_agent == 5);
 195         int pcie_configured  = io_sel >= 2;
 196         struct pci_region *r = hose->regions;
 197
 198         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 199                 printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
 200                         pcie_ep ? "End Point" : "Root Complex",
 201                         (uint)pci);
 202                 if (pci->pme_msg_det) {
 203                         pci->pme_msg_det = 0xffffffff;
 204                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 205                 }
 206                 printf ("\n");
 207
 208                 /* inbound */
 209                 r += fsl_pci_setup_inbound_windows(r);
 210
 211                 /* outbound memory */
 212                 pci_set_region(r++,
 213                                CONFIG_SYS_PCIE1_MEM_BUS,
 214                                CONFIG_SYS_PCIE1_MEM_PHYS,
 215                                CONFIG_SYS_PCIE1_MEM_SIZE,
 216                                PCI_REGION_MEM);
 217
 218                 /* outbound io */
 219                 pci_set_region(r++,
 220                                CONFIG_SYS_PCIE1_IO_BUS,
 221                                CONFIG_SYS_PCIE1_IO_PHYS,
 222                                CONFIG_SYS_PCIE1_IO_SIZE,
 223                                PCI_REGION_IO);
 224
 225 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2
 226                 /* outbound memory */
 227                 pci_set_region(r++,
 228                                CONFIG_SYS_PCIE1_MEM_BUS2,
 229                                CONFIG_SYS_PCIE1_MEM_PHYS2,
 230                                CONFIG_SYS_PCIE1_MEM_SIZE2,
 231                                PCI_REGION_MEM);
 232 #endif
 233                 hose->region_count = r - hose->regions;
 234                 hose->first_busno=first_free_busno;
 235
 236                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 237
 238                 first_free_busno=hose->last_busno+1;
 239                 printf("    PCIE1 on bus %02x - %02x\n",
 240                        hose->first_busno,hose->last_busno);
 241
 242         } else {
 243                 printf ("    PCIE1: disabled\n");
 244         }
 245
 246  }
 247 #else
 248         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 249 #endif
 250
 251 #ifdef CONFIG_PCIE2
 252  {
 253         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 254         struct pci_controller *hose = &pcie2_hose;
 255         int pcie_ep = (host_agent == 3);
 256         int pcie_configured  = io_sel >= 4;
 257         struct pci_region *r = hose->regions;
 258
 259         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 260                 printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 261                         pcie_ep ? "End Point" : "Root Complex",
 262                         (uint)pci);
 263                 if (pci->pme_msg_det) {
 264                         pci->pme_msg_det = 0xffffffff;
 265                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 266                 }
 267                 printf ("\n");
 268
 269                 /* inbound */
 270                 r += fsl_pci_setup_inbound_windows(r);
 271
 272                 /* outbound memory */
 273                 pci_set_region(r++,
 274                                CONFIG_SYS_PCIE2_MEM_BUS,
 275                                CONFIG_SYS_PCIE2_MEM_PHYS,
 276                                CONFIG_SYS_PCIE2_MEM_SIZE,
 277                                PCI_REGION_MEM);
 278
 279                 /* outbound io */
 280                 pci_set_region(r++,
 281                                CONFIG_SYS_PCIE2_IO_BUS,
 282                                CONFIG_SYS_PCIE2_IO_PHYS,
 283                                CONFIG_SYS_PCIE2_IO_SIZE,
 284                                PCI_REGION_IO);
 285
 286 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2
 287                 /* outbound memory */
 288                 pci_set_region(r++,
 289                                CONFIG_SYS_PCIE2_MEM_BUS2,
 290                                CONFIG_SYS_PCIE2_MEM_PHYS2,
 291                                CONFIG_SYS_PCIE2_MEM_SIZE2,
 292                                PCI_REGION_MEM);
 293 #endif
 294                 hose->region_count = r - hose->regions;
 295                 hose->first_busno=first_free_busno;
 296
 297                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 298                 first_free_busno=hose->last_busno+1;
 299                 printf ("    PCIE2 on bus %02x - %02x\n",
 300                         hose->first_busno,hose->last_busno);
 301
 302         } else {
 303                 printf ("    PCIE2: disabled\n");
 304         }
 305
 306  }
 307 #else
 308         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 309 #endif
 310
 311
 312 #ifdef CONFIG_PCI1
 313 {
 314         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 315         struct pci_controller *hose = &pci1_hose;
 316         struct pci_region *r = hose->regions;
 317
 318         uint pci_agent = (host_agent == 6);
 319         uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
 320         uint pci_32 = 1;
 321         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 322         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 323
 324
 325         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 326                 printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
 327                         (pci_32) ? 32 : 64,
 328                         (pci_speed == 33333000) ? "33" :
 329                         (pci_speed == 66666000) ? "66" : "unknown",
 330                         pci_clk_sel ? "sync" : "async",
 331                         pci_agent ? "agent" : "host",
 332                         pci_arb ? "arbiter" : "external-arbiter",
 333                         (uint)pci
 334                         );
 335
 336                 /* inbound */
 337                 r += fsl_pci_setup_inbound_windows(r);
 338
 339                 /* outbound memory */
 340                 pci_set_region(r++,
 341                                CONFIG_SYS_PCI1_MEM_BUS,
 342                                CONFIG_SYS_PCI1_MEM_PHYS,
 343                                CONFIG_SYS_PCI1_MEM_SIZE,
 344                                PCI_REGION_MEM);
 345
 346                 /* outbound io */
 347                 pci_set_region(r++,
 348                                CONFIG_SYS_PCI1_IO_BUS,
 349                                CONFIG_SYS_PCI1_IO_PHYS,
 350                                CONFIG_SYS_PCI1_IO_SIZE,
 351                                PCI_REGION_IO);
 352
 353 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
 354                 /* outbound memory */
 355                 pci_set_region(r++,
 356                                CONFIG_SYS_PCIE3_MEM_BUS2,
 357                                CONFIG_SYS_PCIE3_MEM_PHYS2,
 358                                CONFIG_SYS_PCIE3_MEM_SIZE2,
 359                                PCI_REGION_MEM);
 360 #endif
 361                 hose->region_count = r - hose->regions;
 362                 hose->first_busno=first_free_busno;
 363
 364                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 365                 first_free_busno=hose->last_busno+1;
 366                 printf ("PCI on bus %02x - %02x\n",
 367                         hose->first_busno,hose->last_busno);
 368         } else {
 369                 printf ("    PCI: disabled\n");
 370         }
 371 }
 372 #else
 373         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 374 #endif
 375 }
 376
 377
 378 int last_stage_init(void)
 379 {
 380         return 0;
 381 }
 382
 383
 384 unsigned long
 385 get_board_sys_clk(ulong dummy)
 386 {
 387         u8 i, go_bit, rd_clks;
 388         ulong val = 0;
 389         u8 *pixis_base = (u8 *)PIXIS_BASE;
 390
 391         go_bit = in_8(pixis_base + PIXIS_VCTL);
 392         go_bit &= 0x01;
 393
 394         rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
 395         rd_clks &= 0x1C;
 396
 397         /*
 398          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 399          * should we be using the AUX register. Remember, we also set the
 400          * GO bit to boot from the alternate bank on the on-board flash
 401          */
 402
 403         if (go_bit) {
 404                 if (rd_clks == 0x1c)
 405                         i = in_8(pixis_base + PIXIS_AUX);
 406                 else
 407                         i = in_8(pixis_base + PIXIS_SPD);
 408         } else {
 409                 i = in_8(pixis_base + PIXIS_SPD);
 410         }
 411
 412         i &= 0x07;
 413
 414         switch (i) {
 415         case 0:
 416                 val = 33333333;
 417                 break;
 418         case 1:
 419                 val = 40000000;
 420                 break;
 421         case 2:
 422                 val = 50000000;
 423                 break;
 424         case 3:
 425                 val = 66666666;
 426                 break;
 427         case 4:
 428                 val = 83000000;
 429                 break;
 430         case 5:
 431                 val = 100000000;
 432                 break;
 433         case 6:
 434                 val = 133333333;
 435                 break;
 436         case 7:
 437                 val = 166666666;
 438                 break;
 439         }
 440
 441         return val;
 442 }
 443
 444 int board_eth_init(bd_t *bis)
 445 {
 446 #ifdef CONFIG_TSEC_ENET
 447         struct tsec_info_struct tsec_info[2];
 448         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 449         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 450         int num = 0;
 451
 452 #ifdef CONFIG_TSEC1
 453         SET_STD_TSEC_INFO(tsec_info[num], 1);
 454         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 455                 tsec_info[num].flags |= TSEC_SGMII;
 456         num++;
 457 #endif
 458 #ifdef CONFIG_TSEC3
 459         SET_STD_TSEC_INFO(tsec_info[num], 3);
 460         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 461                 tsec_info[num].flags |= TSEC_SGMII;
 462         num++;
 463 #endif
 464
 465         if (!num) {
 466                 printf("No TSECs initialized\n");
 467
 468                 return 0;
 469         }
 470
 471         if (io_sel & 1)
 472                 fsl_sgmii_riser_init(tsec_info, num);
 473
 474
 475         tsec_eth_init(bis, tsec_info, num);
 476 #endif
 477         return pci_eth_init(bis);
 478 }
 479
 480 #if defined(CONFIG_OF_BOARD_SETUP)
 481 void ft_board_setup(void *blob, bd_t *bd)
 482 {
 483         ft_cpu_setup(blob, bd);
 484
 485
 486 #ifdef CONFIG_PCI1
 487         ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 488 #endif
 489 #ifdef CONFIG_PCIE2
 490         ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
 491 #endif
 492 #ifdef CONFIG_PCIE1
 493         ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
 494 #endif
 495 #ifdef CONFIG_PCIE3
 496         ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
 497 #endif
 498 #ifdef CONFIG_FSL_SGMII_RISER
 499         fsl_sgmii_riser_fdt_fixup(blob);
 500 #endif
 501 }
 502 #endif