board/freescale/mpc8568mds/mpc8568mds.c

   1 /*
   2  * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <pci.h>
  11 #include <asm/processor.h>
  12 #include <asm/mmu.h>
  13 #include <asm/immap_85xx.h>
  14 #include <asm/fsl_pci.h>
  15 #include <asm/fsl_ddr_sdram.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <spd_sdram.h>
  18 #include <i2c.h>
  19 #include <ioports.h>
  20 #include <libfdt.h>
  21 #include <fdt_support.h>
  22
  23 #include "bcsr.h"
  24
  25 const qe_iop_conf_t qe_iop_conf_tab[] = {
  26         /* GETH1 */
  27         {4, 10, 1, 0, 2}, /* TxD0 */
  28         {4,  9, 1, 0, 2}, /* TxD1 */
  29         {4,  8, 1, 0, 2}, /* TxD2 */
  30         {4,  7, 1, 0, 2}, /* TxD3 */
  31         {4, 23, 1, 0, 2}, /* TxD4 */
  32         {4, 22, 1, 0, 2}, /* TxD5 */
  33         {4, 21, 1, 0, 2}, /* TxD6 */
  34         {4, 20, 1, 0, 2}, /* TxD7 */
  35         {4, 15, 2, 0, 2}, /* RxD0 */
  36         {4, 14, 2, 0, 2}, /* RxD1 */
  37         {4, 13, 2, 0, 2}, /* RxD2 */
  38         {4, 12, 2, 0, 2}, /* RxD3 */
  39         {4, 29, 2, 0, 2}, /* RxD4 */
  40         {4, 28, 2, 0, 2}, /* RxD5 */
  41         {4, 27, 2, 0, 2}, /* RxD6 */
  42         {4, 26, 2, 0, 2}, /* RxD7 */
  43         {4, 11, 1, 0, 2}, /* TX_EN */
  44         {4, 24, 1, 0, 2}, /* TX_ER */
  45         {4, 16, 2, 0, 2}, /* RX_DV */
  46         {4, 30, 2, 0, 2}, /* RX_ER */
  47         {4, 17, 2, 0, 2}, /* RX_CLK */
  48         {4, 19, 1, 0, 2}, /* GTX_CLK */
  49         {1, 31, 2, 0, 3}, /* GTX125 */
  50
  51         /* GETH2 */
  52         {5, 10, 1, 0, 2}, /* TxD0 */
  53         {5,  9, 1, 0, 2}, /* TxD1 */
  54         {5,  8, 1, 0, 2}, /* TxD2 */
  55         {5,  7, 1, 0, 2}, /* TxD3 */
  56         {5, 23, 1, 0, 2}, /* TxD4 */
  57         {5, 22, 1, 0, 2}, /* TxD5 */
  58         {5, 21, 1, 0, 2}, /* TxD6 */
  59         {5, 20, 1, 0, 2}, /* TxD7 */
  60         {5, 15, 2, 0, 2}, /* RxD0 */
  61         {5, 14, 2, 0, 2}, /* RxD1 */
  62         {5, 13, 2, 0, 2}, /* RxD2 */
  63         {5, 12, 2, 0, 2}, /* RxD3 */
  64         {5, 29, 2, 0, 2}, /* RxD4 */
  65         {5, 28, 2, 0, 2}, /* RxD5 */
  66         {5, 27, 2, 0, 3}, /* RxD6 */
  67         {5, 26, 2, 0, 2}, /* RxD7 */
  68         {5, 11, 1, 0, 2}, /* TX_EN */
  69         {5, 24, 1, 0, 2}, /* TX_ER */
  70         {5, 16, 2, 0, 2}, /* RX_DV */
  71         {5, 30, 2, 0, 2}, /* RX_ER */
  72         {5, 17, 2, 0, 2}, /* RX_CLK */
  73         {5, 19, 1, 0, 2}, /* GTX_CLK */
  74         {1, 31, 2, 0, 3}, /* GTX125 */
  75         {4,  6, 3, 0, 2}, /* MDIO */
  76         {4,  5, 1, 0, 2}, /* MDC */
  77
  78         /* UART1 */
  79         {2, 0, 1, 0, 2}, /* UART_SOUT1 */
  80         {2, 1, 1, 0, 2}, /* UART_RTS1 */
  81         {2, 2, 2, 0, 2}, /* UART_CTS1 */
  82         {2, 3, 2, 0, 2}, /* UART_SIN1 */
  83
  84         {0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  85 };
  86
  87 void local_bus_init(void);
  88
  89 int board_early_init_f (void)
  90 {
  91         /*
  92          * Initialize local bus.
  93          */
  94         local_bus_init ();
  95
  96         enable_8568mds_duart();
  97         enable_8568mds_flash_write();
  98 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
  99         reset_8568mds_uccs();
 100 #endif
 101 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
 102         enable_8568mds_qe_mdio();
 103 #endif
 104
 105 #ifdef CONFIG_SYS_I2C2_OFFSET
 106         /* Enable I2C2_SCL and I2C2_SDA */
 107         volatile struct par_io *port_c;
 108         port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
 109         port_c->cpdir2 |= 0x0f000000;
 110         port_c->cppar2 &= ~0x0f000000;
 111         port_c->cppar2 |= 0x0a000000;
 112 #endif
 113
 114         return 0;
 115 }
 116
 117 int checkboard (void)
 118 {
 119         printf ("Board: 8568 MDS\n");
 120
 121         return 0;
 122 }
 123
 124 /*
 125  * Initialize Local Bus
 126  */
 127 void
 128 local_bus_init(void)
 129 {
 130         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 131         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 132
 133         uint clkdiv;
 134         sys_info_t sysinfo;
 135
 136         get_sys_info(&sysinfo);
 137         clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
 138
 139         gur->lbiuiplldcr1 = 0x00078080;
 140         if (clkdiv == 16) {
 141                 gur->lbiuiplldcr0 = 0x7c0f1bf0;
 142         } else if (clkdiv == 8) {
 143                 gur->lbiuiplldcr0 = 0x6c0f1bf0;
 144         } else if (clkdiv == 4) {
 145                 gur->lbiuiplldcr0 = 0x5c0f1bf0;
 146         }
 147
 148         lbc->lcrr |= 0x00030000;
 149
 150         asm("sync;isync;msync");
 151 }
 152
 153 /*
 154  * Initialize SDRAM memory on the Local Bus.
 155  */
 156 void lbc_sdram_init(void)
 157 {
 158 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 159
 160         uint idx;
 161         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 162         uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 163         uint lsdmr_common;
 164
 165         puts("LBC SDRAM: ");
 166         print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
 167                    "\n       ");
 168
 169         /*
 170          * Setup SDRAM Base and Option Registers
 171          */
 172         set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
 173         set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 174         asm("msync");
 175
 176         lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 177         asm("msync");
 178
 179         lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 180         lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 181         asm("msync");
 182
 183         /*
 184          * MPC8568 uses "new" 15-16 style addressing.
 185          */
 186         lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 187         lsdmr_common |= LSDMR_BSMA1516;
 188
 189         /*
 190          * Issue PRECHARGE ALL command.
 191          */
 192         lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 193         asm("sync;msync");
 194         *sdram_addr = 0xff;
 195         ppcDcbf((unsigned long) sdram_addr);
 196         udelay(100);
 197
 198         /*
 199          * Issue 8 AUTO REFRESH commands.
 200          */
 201         for (idx = 0; idx < 8; idx++) {
 202                 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 203                 asm("sync;msync");
 204                 *sdram_addr = 0xff;
 205                 ppcDcbf((unsigned long) sdram_addr);
 206                 udelay(100);
 207         }
 208
 209         /*
 210          * Issue 8 MODE-set command.
 211          */
 212         lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 213         asm("sync;msync");
 214         *sdram_addr = 0xff;
 215         ppcDcbf((unsigned long) sdram_addr);
 216         udelay(100);
 217
 218         /*
 219          * Issue NORMAL OP command.
 220          */
 221         lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 222         asm("sync;msync");
 223         *sdram_addr = 0xff;
 224         ppcDcbf((unsigned long) sdram_addr);
 225         udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 226
 227 #endif  /* enable SDRAM init */
 228 }
 229
 230 #if defined(CONFIG_PCI)
 231 #ifndef CONFIG_PCI_PNP
 232 static struct pci_config_table pci_mpc8568mds_config_table[] = {
 233         {
 234          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 235          pci_cfgfunc_config_device,
 236          {PCI_ENET0_IOADDR,
 237           PCI_ENET0_MEMADDR,
 238           PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
 239          },
 240         {}
 241 };
 242 #endif
 243
 244 static struct pci_controller pci1_hose;
 245 #endif  /* CONFIG_PCI */
 246
 247 /*
 248  * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
 249  */
 250 void
 251 pib_init(void)
 252 {
 253         u8 val8, orig_i2c_bus;
 254         /*
 255          * Assign PIB PMC2/3 to PCI bus
 256          */
 257
 258         /*switch temporarily to I2C bus #2 */
 259         orig_i2c_bus = i2c_get_bus_num();
 260         i2c_set_bus_num(1);
 261
 262         val8 = 0x00;
 263         i2c_write(0x23, 0x6, 1, &val8, 1);
 264         i2c_write(0x23, 0x7, 1, &val8, 1);
 265         val8 = 0xff;
 266         i2c_write(0x23, 0x2, 1, &val8, 1);
 267         i2c_write(0x23, 0x3, 1, &val8, 1);
 268
 269         val8 = 0x00;
 270         i2c_write(0x26, 0x6, 1, &val8, 1);
 271         val8 = 0x34;
 272         i2c_write(0x26, 0x7, 1, &val8, 1);
 273         val8 = 0xf9;
 274         i2c_write(0x26, 0x2, 1, &val8, 1);
 275         val8 = 0xff;
 276         i2c_write(0x26, 0x3, 1, &val8, 1);
 277
 278         val8 = 0x00;
 279         i2c_write(0x27, 0x6, 1, &val8, 1);
 280         i2c_write(0x27, 0x7, 1, &val8, 1);
 281         val8 = 0xff;
 282         i2c_write(0x27, 0x2, 1, &val8, 1);
 283         val8 = 0xef;
 284         i2c_write(0x27, 0x3, 1, &val8, 1);
 285
 286         asm("eieio");
 287         i2c_set_bus_num(orig_i2c_bus);
 288 }
 289
 290 #ifdef CONFIG_PCI
 291 void pci_init_board(void)
 292 {
 293         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 294         int first_free_busno = 0;
 295 #ifdef CONFIG_PCI1
 296         struct fsl_pci_info pci_info;
 297         u32 devdisr, pordevsr, io_sel;
 298         u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
 299
 300         devdisr = in_be32(&gur->devdisr);
 301         pordevsr = in_be32(&gur->pordevsr);
 302         porpllsr = in_be32(&gur->porpllsr);
 303         io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 304
 305         debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 306
 307         pci_speed = 66666000;
 308         pci_32 = 1;
 309         pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 310         pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 311
 312         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 313                 SET_STD_PCI_INFO(pci_info, 1);
 314                 set_next_law(pci_info.mem_phys,
 315                         law_size_bits(pci_info.mem_size), pci_info.law);
 316                 set_next_law(pci_info.io_phys,
 317                         law_size_bits(pci_info.io_size), pci_info.law);
 318
 319                 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 320                 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 321                         (pci_32) ? 32 : 64,
 322                         (pci_speed == 33333000) ? "33" :
 323                         (pci_speed == 66666000) ? "66" : "unknown",
 324                         pci_clk_sel ? "sync" : "async",
 325                         pci_agent ? "agent" : "host",
 326                         pci_arb ? "arbiter" : "external-arbiter",
 327                         pci_info.regs);
 328
 329 #ifndef CONFIG_PCI_PNP
 330                 pci1_hose.config_table = pci_mpc8568mds_config_table;
 331 #endif
 332                 first_free_busno = fsl_pci_init_port(&pci_info,
 333                                         &pci1_hose, first_free_busno);
 334         } else {
 335                 printf("PCI: disabled\n");
 336         }
 337
 338         puts("\n");
 339 #else
 340         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 341 #endif
 342
 343         fsl_pcie_init_board(first_free_busno);
 344 }
 345 #endif /* CONFIG_PCI */
 346
 347 #if defined(CONFIG_OF_BOARD_SETUP)
 348 void ft_board_setup(void *blob, bd_t *bd)
 349 {
 350         ft_cpu_setup(blob, bd);
 351
 352         FT_FSL_PCI_SETUP;
 353 }
 354 #endif