board/freescale/mpc8610hpcd/mpc8610hpcd.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 #define DEBUG
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/immap_86xx.h>
  28 #include <asm/immap_fsl_pci.h>
  29 #include <spd.h>
  30 #include <asm/io.h>
  31
  32
  33 #if defined(CONFIG_OF_FLAT_TREE)
  34 #include <ft_build.h>
  35 extern void ft_cpu_setup(void *blob, bd_t *bd);
  36 #endif
  37
  38 #include "../common/pixis.h"
  39
  40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  41 extern void ddr_enable_ecc(unsigned int dram_size);
  42 #endif
  43
  44 #if defined(CONFIG_SPD_EEPROM)
  45 #include "spd_sdram.h"
  46 #endif
  47
  48 void sdram_init(void);
  49 long int fixed_sdram(void);
  50
  51 /* called before any console output */
  52 int board_early_init_f(void)
  53 {
  54         volatile immap_t *immap = (immap_t *)CFG_IMMR;
  55         volatile ccsr_gur_t *gur = &immap->im_gur;
  56
  57         gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
  58
  59         return 0;
  60 }
  61
  62 int misc_init_r(void)
  63 {
  64         u8 tmp_val, version;
  65
  66         /*Do not use 8259PIC*/
  67         tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
  68         out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
  69
  70         /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
  71         version = in8(PIXIS_BASE + PIXIS_PVER);
  72         if(version >= 0x07) {
  73                 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
  74                 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
  75         }
  76
  77         /* Using this for DIU init before the driver in linux takes over
  78          *  Enable the TFP410 Encoder (I2C address 0x38)
  79          */
  80
  81         tmp_val = 0xBF;
  82         i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  83         /* Verify if enabled */
  84         tmp_val = 0;
  85         i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  86         debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
  87
  88         tmp_val = 0x10;
  89         i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  90         /* Verify if enabled */
  91         tmp_val = 0;
  92         i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  93         debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
  94
  95 #ifdef CONFIG_FSL_DIU_FB
  96         mpc8610hpcd_diu_init();
  97 #endif
  98
  99         return 0;
 100 }
 101
 102 int checkboard(void)
 103 {
 104         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 105         volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
 106
 107         puts("Board: MPC8610HPCD\n");
 108
 109         mcm->abcr |= 0x00010000; /* 0 */
 110         mcm->hpmr3 = 0x80000008; /* 4c */
 111         mcm->hpmr0 = 0;
 112         mcm->hpmr1 = 0;
 113         mcm->hpmr2 = 0;
 114         mcm->hpmr4 = 0;
 115         mcm->hpmr5 = 0;
 116
 117         return 0;
 118 }
 119
 120
 121 long int
 122 initdram(int board_type)
 123 {
 124         long dram_size = 0;
 125
 126 #if defined(CONFIG_SPD_EEPROM)
 127         dram_size = spd_sdram();
 128 #else
 129         dram_size = fixed_sdram();
 130 #endif
 131
 132 #if defined(CFG_RAMBOOT)
 133         puts(" DDR: ");
 134         return dram_size;
 135 #endif
 136
 137 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 138         /*
 139          * Initialize and enable DDR ECC.
 140          */
 141         ddr_enable_ecc(dram_size);
 142 #endif
 143
 144         puts(" DDR: ");
 145         return dram_size;
 146 }
 147
 148
 149 #if defined(CFG_DRAM_TEST)
 150 int
 151 testdram(void)
 152 {
 153         uint *pstart = (uint *) CFG_MEMTEST_START;
 154         uint *pend = (uint *) CFG_MEMTEST_END;
 155         uint *p;
 156
 157         puts("SDRAM test phase 1:\n");
 158         for (p = pstart; p < pend; p++)
 159                 *p = 0xaaaaaaaa;
 160
 161         for (p = pstart; p < pend; p++) {
 162                 if (*p != 0xaaaaaaaa) {
 163                         printf("SDRAM test fails at: %08x\n", (uint) p);
 164                         return 1;
 165                 }
 166         }
 167
 168         puts("SDRAM test phase 2:\n");
 169         for (p = pstart; p < pend; p++)
 170                 *p = 0x55555555;
 171
 172         for (p = pstart; p < pend; p++) {
 173                 if (*p != 0x55555555) {
 174                         printf("SDRAM test fails at: %08x\n", (uint) p);
 175                         return 1;
 176                 }
 177         }
 178
 179         puts("SDRAM test passed.\n");
 180         return 0;
 181 }
 182 #endif
 183
 184
 185 #if !defined(CONFIG_SPD_EEPROM)
 186 /*
 187  * Fixed sdram init -- doesn't use serial presence detect.
 188  */
 189
 190 long int fixed_sdram(void)
 191 {
 192 #if !defined(CFG_RAMBOOT)
 193         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 194         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 195         uint d_init;
 196
 197         ddr->cs0_bnds = 0x0000001f;
 198         ddr->cs0_config = 0x80010202;
 199
 200         ddr->ext_refrec = 0x00000000;
 201         ddr->timing_cfg_0 = 0x00260802;
 202         ddr->timing_cfg_1 = 0x3935d322;
 203         ddr->timing_cfg_2 = 0x14904cc8;
 204         ddr->sdram_mode_1 = 0x00480432;
 205         ddr->sdram_mode_2 = 0x00000000;
 206         ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
 207         ddr->sdram_data_init = 0xDEADBEEF;
 208         ddr->sdram_clk_cntl = 0x03800000;
 209         ddr->sdram_cfg_2 = 0x04400010;
 210
 211 #if defined(CONFIG_DDR_ECC)
 212         ddr->err_int_en = 0x0000000d;
 213         ddr->err_disable = 0x00000000;
 214         ddr->err_sbe = 0x00010000;
 215 #endif
 216         asm("sync;isync");
 217
 218         udelay(500);
 219
 220         ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
 221
 222
 223 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 224         d_init = 1;
 225         debug("DDR - 1st controller: memory initializing\n");
 226         /*
 227          * Poll until memory is initialized.
 228          * 512 Meg at 400 might hit this 200 times or so.
 229          */
 230         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 231                 udelay(1000);
 232
 233         debug("DDR: memory initialized\n\n");
 234         asm("sync; isync");
 235         udelay(500);
 236 #endif
 237
 238         return 512 * 1024 * 1024;
 239 #endif
 240         return CFG_SDRAM_SIZE * 1024 * 1024;
 241 }
 242
 243 #endif
 244
 245 #if defined(CONFIG_PCI)
 246 /*
 247  * Initialize PCI Devices, report devices found.
 248  */
 249
 250 #ifndef CONFIG_PCI_PNP
 251 static struct pci_config_table pci_fsl86xxads_config_table[] = {
 252         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 253          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 254          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 255                                  PCI_ENET0_MEMADDR,
 256                                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
 257         {}
 258 };
 259 #endif
 260
 261
 262 static struct pci_controller pci1_hose = {
 263 #ifndef CONFIG_PCI_PNP
 264 config_table:pci_mpc86xxcts_config_table
 265 #endif
 266 };
 267 #endif /* CONFIG_PCI */
 268
 269 #ifdef CONFIG_PCIE1
 270 static struct pci_controller pcie1_hose;
 271 #endif
 272
 273 #ifdef CONFIG_PCIE2
 274 static struct pci_controller pcie2_hose;
 275 #endif
 276
 277 int first_free_busno = 0;
 278
 279 void pci_init_board(void)
 280 {
 281         volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
 282         volatile ccsr_gur_t *gur = &immap->im_gur;
 283         uint devdisr = gur->devdisr;
 284         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 285         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 286
 287         printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 288                 devdisr, io_sel, host_agent);
 289
 290
 291 #ifdef CONFIG_PCIE1
 292  {
 293         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
 294         extern void fsl_pci_init(struct pci_controller *hose);
 295         struct pci_controller *hose = &pcie1_hose;
 296         int pcie_configured = (io_sel == 1) || (io_sel == 4);
 297         int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
 298                 (host_agent == 5);
 299
 300         if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
 301                 printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
 302                         pcie_ep ? "End Point" : "Root Complex",
 303                         (uint)pci);
 304                 if (pci->pme_msg_det)
 305                         pci->pme_msg_det = 0xffffffff;
 306
 307                 /* inbound */
 308                 pci_set_region(hose->regions + 0,
 309                          CFG_PCI_MEMORY_BUS,
 310                          CFG_PCI_MEMORY_PHYS,
 311                          CFG_PCI_MEMORY_SIZE,
 312                          PCI_REGION_MEM | PCI_REGION_MEMORY);
 313
 314                 /* outbound memory */
 315                 pci_set_region(hose->regions + 1,
 316                          CFG_PCIE1_MEM_BASE,
 317                          CFG_PCIE1_MEM_PHYS,
 318                          CFG_PCIE1_MEM_SIZE,
 319                          PCI_REGION_MEM);
 320
 321                 /* outbound io */
 322                 pci_set_region(hose->regions + 2,
 323                          CFG_PCIE1_IO_BASE,
 324                          CFG_PCIE1_IO_PHYS,
 325                          CFG_PCIE1_IO_SIZE,
 326                          PCI_REGION_IO);
 327
 328                 hose->region_count = 3;
 329
 330                 hose->first_busno = first_free_busno;
 331                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 332                                  (int)&pci->cfg_data);
 333
 334                 fsl_pci_init(hose);
 335
 336                 first_free_busno = hose->last_busno + 1;
 337                 printf(" PCI-Express 1 on bus %02x - %02x\n",
 338                         hose->first_busno, hose->last_busno);
 339
 340         } else
 341                 puts(" PCI-Express 1: Disabled\n");
 342  }
 343 #else
 344         puts("PCI-Express 1: Disabled\n");
 345 #endif /* CONFIG_PCIE1 */
 346
 347
 348 #ifdef CONFIG_PCIE2
 349  {
 350         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
 351         extern void fsl_pci_init(struct pci_controller *hose);
 352         struct pci_controller *hose = &pcie2_hose;
 353
 354         int pcie_configured = (io_sel == 0) || (io_sel == 4);
 355         int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
 356                 (host_agent == 4);
 357
 358         if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
 359                 printf(" PCI-Express 2 connected to slot as %s" \
 360                         " (base address %x)\n",
 361                         pcie_ep ? "End Point" : "Root Complex",
 362                         (uint)pci);
 363                 if (pci->pme_msg_det)
 364                         pci->pme_msg_det = 0xffffffff;
 365
 366                 /* inbound */
 367                 pci_set_region(hose->regions + 0,
 368                          CFG_PCI_MEMORY_BUS,
 369                          CFG_PCI_MEMORY_PHYS,
 370                          CFG_PCI_MEMORY_SIZE,
 371                          PCI_REGION_MEM | PCI_REGION_MEMORY);
 372
 373                 /* outbound memory */
 374                 pci_set_region(hose->regions + 1,
 375                          CFG_PCIE2_MEM_BASE,
 376                          CFG_PCIE2_MEM_PHYS,
 377                          CFG_PCIE2_MEM_SIZE,
 378                          PCI_REGION_MEM);
 379
 380                 /* outbound io */
 381                 pci_set_region(hose->regions + 2,
 382                          CFG_PCIE2_IO_BASE,
 383                          CFG_PCIE2_IO_PHYS,
 384                          CFG_PCIE2_IO_SIZE,
 385                          PCI_REGION_IO);
 386
 387                 hose->region_count = 3;
 388
 389                 hose->first_busno = first_free_busno;
 390                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 391                                  (int)&pci->cfg_data);
 392
 393                 fsl_pci_init(hose);
 394
 395                 first_free_busno = hose->last_busno + 1;
 396                 printf(" PCI-Express 2 on bus %02x - %02x\n",
 397                         hose->first_busno, hose->last_busno);
 398         } else
 399                 puts(" PCI-Express 2: Disabled\n");
 400  }
 401 #else
 402         puts("PCI-Express 2: Disabled\n");
 403 #endif /* CONFIG_PCIE2 */
 404
 405
 406 #ifdef CONFIG_PCI1
 407  {
 408         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 409         extern void fsl_pci_init(struct pci_controller *hose);
 410         struct pci_controller *hose = &pci1_hose;
 411         int pci_agent = (host_agent >= 4) && (host_agent <= 6);
 412
 413         if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
 414                 printf(" PCI connected to PCI slots as %s" \
 415                         " (base address %x)\n",
 416                         pci_agent ? "Agent" : "Host",
 417                         (uint)pci);
 418
 419                 /* inbound */
 420                 pci_set_region(hose->regions + 0,
 421                          CFG_PCI_MEMORY_BUS,
 422                          CFG_PCI_MEMORY_PHYS,
 423                          CFG_PCI_MEMORY_SIZE,
 424                          PCI_REGION_MEM | PCI_REGION_MEMORY);
 425
 426                 /* outbound memory */
 427                 pci_set_region(hose->regions + 1,
 428                          CFG_PCI1_MEM_BASE,
 429                          CFG_PCI1_MEM_PHYS,
 430                          CFG_PCI1_MEM_SIZE,
 431                          PCI_REGION_MEM);
 432
 433                 /* outbound io */
 434                 pci_set_region(hose->regions + 2,
 435                          CFG_PCI1_IO_BASE,
 436                          CFG_PCI1_IO_PHYS,
 437                          CFG_PCI1_IO_SIZE,
 438                          PCI_REGION_IO);
 439
 440                 hose->region_count = 3;
 441
 442                 hose->first_busno = first_free_busno;
 443                 pci_setup_indirect(hose, (int) &pci->cfg_addr,
 444                                  (int) &pci->cfg_data);
 445
 446                 fsl_pci_init(hose);
 447
 448                 first_free_busno = hose->last_busno + 1;
 449                 printf(" PCI on bus %02x - %02x\n",
 450                         hose->first_busno, hose->last_busno);
 451
 452
 453         } else
 454                 puts(" PCI: Disabled\n");
 455  }
 456 #endif /* CONFIG_PCI1 */
 457 }
 458
 459 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 460 void
 461 ft_board_setup(void *blob, bd_t *bd)
 462 {
 463         u32 *p;
 464         int len;
 465
 466         ft_cpu_setup(blob, bd);
 467
 468         p = ft_get_prop(blob, "/memory/reg", &len);
 469         if (p != NULL) {
 470                 *p++ = cpu_to_be32(bd->bi_memstart);
 471                 *p = cpu_to_be32(bd->bi_memsize);
 472         }
 473
 474 #ifdef CONFIG_PCI1
 475         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
 476         if (p != NULL) {
 477                 p[0] = 0;
 478                 p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 479                 debug("pci@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 480         }
 481 #endif
 482 #ifdef CONFIG_PCIE1
 483         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
 484         if (p != NULL) {
 485                 p[0] = 0;
 486                 p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 487                 debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 488         }
 489 #endif
 490 #ifdef CONFIG_PCIE2
 491         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
 492         if (p != NULL) {
 493                 p[0] = 0;
 494                 p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
 495                 debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 496         }
 497 #endif
 498
 499 }
 500 #endif
 501
 502 /*
 503  * get_board_sys_clk
 504  * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 505  */
 506
 507 unsigned long
 508 get_board_sys_clk(ulong dummy)
 509 {
 510         u8 i;
 511         ulong val = 0;
 512         ulong a;
 513
 514         a = PIXIS_BASE + PIXIS_SPD;
 515         i = in8(a);
 516         i &= 0x07;
 517
 518         switch (i) {
 519         case 0:
 520                 val = 33333000;
 521                 break;
 522         case 1:
 523                 val = 39999600;
 524                 break;
 525         case 2:
 526                 val = 49999500;
 527                 break;
 528         case 3:
 529                 val = 66666000;
 530                 break;
 531         case 4:
 532                 val = 83332500;
 533                 break;
 534         case 5:
 535                 val = 99999000;
 536                 break;
 537         case 6:
 538                 val = 133332000;
 539                 break;
 540         case 7:
 541                 val = 166665000;
 542                 break;
 543         }
 544
 545         return val;
 546 }