2 * Copyright 2008,2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
9 #include <fsl_ddr_sdram.h>
10 #include <fsl_ddr_dimm_params.h>
12 struct board_specific_parameters
{
14 u32 datarate_mhz_high
;
21 * This table contains all valid speeds we want to override with board
22 * specific parameters. datarate_mhz_high values need to be in ascending order
23 * for each n_ranks group.
25 const struct board_specific_parameters dimm0
[] = {
28 * num| hi| clk| cpo|wrdata|2T
29 * ranks| mhz|adjst| | delay|
44 * The two slots have slightly different timing. The center values are good
45 * for both slots. We use identical speed tables for them. In future use, if
46 * DIMMs have fewer center values that require two separated tables, copy the
47 * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
49 const struct board_specific_parameters
*dimms
[] = {
54 void fsl_ddr_board_options(memctl_options_t
*popts
,
56 unsigned int ctrl_num
)
58 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
63 printf("Wrong parameter for controller number %d", ctrl_num
);
66 for (i
= 0; i
< CONFIG_DIMM_SLOTS_PER_CTLR
; i
++) {
70 if (i
>= CONFIG_DIMM_SLOTS_PER_CTLR
) /* no DIMM */
73 pbsp
= dimms
[ctrl_num
];
75 /* Get clk_adjust, cpo, write_data_delay, according to the board ddr
76 * freqency and n_banks specified in board_specific_parameters table.
78 ddr_freq
= get_ddr_freq(0) / 1000000;
79 while (pbsp
->datarate_mhz_high
) {
80 if (pbsp
->n_ranks
== pdimm
[i
].n_ranks
) {
81 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
82 popts
->clk_adjust
= pbsp
->clk_adjust
;
83 popts
->cpo_override
= pbsp
->cpo
;
84 popts
->write_data_delay
=
85 pbsp
->write_data_delay
;
94 printf("Error: board specific timing not found "
95 "for data rate %lu MT/s!\n"
96 "Trying to use the highest speed (%u) parameters\n",
97 ddr_freq
, pbsp_highest
->datarate_mhz_high
);
98 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
99 popts
->cpo_override
= pbsp_highest
->cpo
;
100 popts
->write_data_delay
= pbsp_highest
->write_data_delay
;
102 panic("DIMM is not supported by this board");
106 /* 2T timing enable */