board/freescale/mpc8641hpcn/mpc8641hpcn.c

   1 /*
   2  * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <pci.h>
   9 #include <asm/processor.h>
  10 #include <asm/immap_86xx.h>
  11 #include <asm/fsl_pci.h>
  12 #include <fsl_ddr_sdram.h>
  13 #include <asm/fsl_serdes.h>
  14 #include <asm/io.h>
  15 #include <libfdt.h>
  16 #include <fdt_support.h>
  17 #include <netdev.h>
  18
  19 phys_size_t fixed_sdram(void);
  20
  21 int checkboard(void)
  22 {
  23         u8 vboot;
  24         u8 *pixis_base = (u8 *)PIXIS_BASE;
  25
  26         printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
  27                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  28                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  29                 in_8(pixis_base + PIXIS_PVER));
  30
  31         vboot = in_8(pixis_base + PIXIS_VBOOT);
  32         if (vboot & PIXIS_VBOOT_FMAP)
  33                 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
  34         else
  35                 puts ("Promjet\n");
  36
  37         return 0;
  38 }
  39
  40 phys_size_t
  41 initdram(int board_type)
  42 {
  43         phys_size_t dram_size = 0;
  44
  45 #if defined(CONFIG_SPD_EEPROM)
  46         dram_size = fsl_ddr_sdram();
  47 #else
  48         dram_size = fixed_sdram();
  49 #endif
  50
  51         setup_ddr_bat(dram_size);
  52
  53         debug("    DDR: ");
  54         return dram_size;
  55 }
  56
  57
  58 #if !defined(CONFIG_SPD_EEPROM)
  59 /*
  60  * Fixed sdram init -- doesn't use serial presence detect.
  61  */
  62 phys_size_t
  63 fixed_sdram(void)
  64 {
  65 #if !defined(CONFIG_SYS_RAMBOOT)
  66         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  67         struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
  68
  69         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  70         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  71         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  72         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  73         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  74         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  75         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  76         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  77         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  78         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  79         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  80         ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
  81         ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
  82
  83 #if defined (CONFIG_DDR_ECC)
  84         ddr->err_disable = 0x0000008D;
  85         ddr->err_sbe = 0x00ff0000;
  86 #endif
  87         asm("sync;isync");
  88
  89         udelay(500);
  90
  91 #if defined (CONFIG_DDR_ECC)
  92         /* Enable ECC checking */
  93         ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
  94 #else
  95         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
  96         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
  97 #endif
  98         asm("sync; isync");
  99
 100         udelay(500);
 101 #endif
 102         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 103 }
 104 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 105
 106 void pci_init_board(void)
 107 {
 108         fsl_pcie_init_board(0);
 109
 110 #ifdef CONFIG_PCIE1
 111                 /*
 112                  * Activate ULI1575 legacy chip by performing a fake
 113                  * memory access.  Needed to make ULI RTC work.
 114                  */
 115                 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
 116                                        + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
 117 #endif /* CONFIG_PCIE1 */
 118 }
 119
 120
 121 #if defined(CONFIG_OF_BOARD_SETUP)
 122 int ft_board_setup(void *blob, bd_t *bd)
 123 {
 124         int off;
 125         u64 *tmp;
 126         u32 *addrcells;
 127
 128         ft_cpu_setup(blob, bd);
 129
 130         FT_FSL_PCI_SETUP;
 131
 132         /*
 133          * Warn if it looks like the device tree doesn't match u-boot.
 134          * This is just an estimation, based on the location of CCSR,
 135          * which is defined by the "reg" property in the soc node.
 136          */
 137         off = fdt_path_offset(blob, "/soc8641");
 138         addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
 139         tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
 140
 141         if (tmp) {
 142                 u64 addr;
 143                 if (addrcells && (*addrcells == 1))
 144                         addr = *(u32 *)tmp;
 145                 else
 146                         addr = *tmp;
 147
 148                 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
 149                         printf("WARNING: The CCSRBAR address in your .dts "
 150                                "does not match the address of the CCSR "
 151                                "in u-boot.  This means your .dts might "
 152                                "be old.\n");
 153         }
 154
 155         return 0;
 156 }
 157 #endif
 158
 159
 160 /*
 161  * get_board_sys_clk
 162  *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 163  */
 164
 165 unsigned long
 166 get_board_sys_clk(ulong dummy)
 167 {
 168         u8 i, go_bit, rd_clks;
 169         ulong val = 0;
 170         u8 *pixis_base = (u8 *)PIXIS_BASE;
 171
 172         go_bit = in_8(pixis_base + PIXIS_VCTL);
 173         go_bit &= 0x01;
 174
 175         rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
 176         rd_clks &= 0x1C;
 177
 178         /*
 179          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 180          * should we be using the AUX register. Remember, we also set the
 181          * GO bit to boot from the alternate bank on the on-board flash
 182          */
 183
 184         if (go_bit) {
 185                 if (rd_clks == 0x1c)
 186                         i = in_8(pixis_base + PIXIS_AUX);
 187                 else
 188                         i = in_8(pixis_base + PIXIS_SPD);
 189         } else {
 190                 i = in_8(pixis_base + PIXIS_SPD);
 191         }
 192
 193         i &= 0x07;
 194
 195         switch (i) {
 196         case 0:
 197                 val = 33000000;
 198                 break;
 199         case 1:
 200                 val = 40000000;
 201                 break;
 202         case 2:
 203                 val = 50000000;
 204                 break;
 205         case 3:
 206                 val = 66000000;
 207                 break;
 208         case 4:
 209                 val = 83000000;
 210                 break;
 211         case 5:
 212                 val = 100000000;
 213                 break;
 214         case 6:
 215                 val = 134000000;
 216                 break;
 217         case 7:
 218                 val = 166000000;
 219                 break;
 220         }
 221
 222         return val;
 223 }
 224
 225 int board_eth_init(bd_t *bis)
 226 {
 227         /* Initialize TSECs */
 228         cpu_eth_init(bis);
 229         return pci_eth_init(bis);
 230 }
 231
 232 void board_reset(void)
 233 {
 234         u8 *pixis_base = (u8 *)PIXIS_BASE;
 235
 236         out_8(pixis_base + PIXIS_RST, 0);
 237
 238         while (1)
 239                 ;
 240 }