board/freescale/mpc8641hpcn/mpc8641hpcn.c

   1 /*
   2  * Copyright 2006, 2007 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <pci.h>
  25 #include <asm/processor.h>
  26 #include <asm/immap_86xx.h>
  27 #include <asm/immap_fsl_pci.h>
  28 #include <asm/fsl_ddr_sdram.h>
  29 #include <asm/io.h>
  30 #include <libfdt.h>
  31 #include <fdt_support.h>
  32 #include <netdev.h>
  33
  34 #include "../common/pixis.h"
  35
  36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  37 extern void ddr_enable_ecc(unsigned int dram_size);
  38 #endif
  39
  40 long int fixed_sdram(void);
  41
  42 int board_early_init_f(void)
  43 {
  44         return 0;
  45 }
  46
  47 int checkboard(void)
  48 {
  49         printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
  50                 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
  51                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  52                 in8(PIXIS_BASE + PIXIS_PVER));
  53         return 0;
  54 }
  55
  56
  57 phys_size_t
  58 initdram(int board_type)
  59 {
  60         long dram_size = 0;
  61
  62 #if defined(CONFIG_SPD_EEPROM)
  63         dram_size = fsl_ddr_sdram();
  64 #else
  65         dram_size = fixed_sdram();
  66 #endif
  67
  68 #if defined(CONFIG_SYS_RAMBOOT)
  69         puts("    DDR: ");
  70         return dram_size;
  71 #endif
  72
  73 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  74         /*
  75          * Initialize and enable DDR ECC.
  76          */
  77         ddr_enable_ecc(dram_size);
  78 #endif
  79
  80         puts("    DDR: ");
  81         return dram_size;
  82 }
  83
  84
  85 #if !defined(CONFIG_SPD_EEPROM)
  86 /*
  87  * Fixed sdram init -- doesn't use serial presence detect.
  88  */
  89 long int
  90 fixed_sdram(void)
  91 {
  92 #if !defined(CONFIG_SYS_RAMBOOT)
  93         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  94         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
  95
  96         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  97         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  98         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  99         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 100         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 101         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 102         ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
 103         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 104         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 105         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 106         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 107         ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
 108         ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
 109
 110 #if defined (CONFIG_DDR_ECC)
 111         ddr->err_disable = 0x0000008D;
 112         ddr->err_sbe = 0x00ff0000;
 113 #endif
 114         asm("sync;isync");
 115
 116         udelay(500);
 117
 118 #if defined (CONFIG_DDR_ECC)
 119         /* Enable ECC checking */
 120         ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 121 #else
 122         ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
 123         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 124 #endif
 125         asm("sync; isync");
 126
 127         udelay(500);
 128 #endif
 129         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 130 }
 131 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 132
 133
 134 #if defined(CONFIG_PCI)
 135 /*
 136  * Initialize PCI Devices, report devices found.
 137  */
 138
 139 #ifndef CONFIG_PCI_PNP
 140 static struct pci_config_table pci_fsl86xxads_config_table[] = {
 141         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 142          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 143          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 144                                      PCI_ENET0_MEMADDR,
 145                                      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
 146         {}
 147 };
 148 #endif
 149
 150
 151 static struct pci_controller pci1_hose = {
 152 #ifndef CONFIG_PCI_PNP
 153         config_table:pci_mpc86xxcts_config_table
 154 #endif
 155 };
 156 #endif /* CONFIG_PCI */
 157
 158 #ifdef CONFIG_PCI2
 159 static struct pci_controller pci2_hose;
 160 #endif  /* CONFIG_PCI2 */
 161
 162 int first_free_busno = 0;
 163
 164 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
 165 extern void fsl_pci_init(struct pci_controller *hose);
 166
 167 void pci_init_board(void)
 168 {
 169         volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 170         volatile ccsr_gur_t *gur = &immap->im_gur;
 171         uint devdisr = gur->devdisr;
 172         uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
 173                 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 174
 175 #ifdef CONFIG_PCI1
 176 {
 177         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 178         struct pci_controller *hose = &pci1_hose;
 179         struct pci_region *r = hose->regions;
 180
 181 #ifdef DEBUG
 182         uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
 183                 >> MPC8641_PORBMSR_HA_SHIFT;
 184         uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
 185 #endif
 186         if ((io_sel == 2 || io_sel == 3 || io_sel == 5
 187              || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
 188             && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
 189                 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
 190                 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
 191                 if (pci->pme_msg_det) {
 192                         pci->pme_msg_det = 0xffffffff;
 193                         debug(" with errors.  Clearing.  Now 0x%08x",
 194                               pci->pme_msg_det);
 195                 }
 196                 debug("\n");
 197
 198                 /* inbound */
 199                 r += fsl_pci_setup_inbound_windows(r);
 200
 201                 /* outbound memory */
 202                 pci_set_region(r++,
 203                                CONFIG_SYS_PCI1_MEM_BASE,
 204                                CONFIG_SYS_PCI1_MEM_PHYS,
 205                                CONFIG_SYS_PCI1_MEM_SIZE,
 206                                PCI_REGION_MEM);
 207
 208                 /* outbound io */
 209                 pci_set_region(r++,
 210                                CONFIG_SYS_PCI1_IO_BASE,
 211                                CONFIG_SYS_PCI1_IO_PHYS,
 212                                CONFIG_SYS_PCI1_IO_SIZE,
 213                                PCI_REGION_IO);
 214
 215                 hose->region_count = r - hose->regions;
 216
 217                 hose->first_busno=first_free_busno;
 218                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 219
 220                 fsl_pci_init(hose);
 221
 222                 first_free_busno=hose->last_busno+1;
 223                 printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
 224                         hose->first_busno,hose->last_busno);
 225
 226                 /*
 227                  * Activate ULI1575 legacy chip by performing a fake
 228                  * memory access.  Needed to make ULI RTC work.
 229                  */
 230                 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_BASE
 231                                        + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
 232
 233         } else {
 234                 puts("PCI-EXPRESS 1: Disabled\n");
 235         }
 236 }
 237 #else
 238         puts("PCI-EXPRESS1: Disabled\n");
 239 #endif /* CONFIG_PCI1 */
 240
 241 #ifdef CONFIG_PCI2
 242 {
 243         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
 244         struct pci_controller *hose = &pci2_hose;
 245         struct pci_region *r = hose->regions;
 246
 247         /* inbound */
 248         r += fsl_pci_setup_inbound_windows(r);
 249
 250         /* outbound memory */
 251         pci_set_region(r++,
 252                        CONFIG_SYS_PCI2_MEM_BASE,
 253                        CONFIG_SYS_PCI2_MEM_PHYS,
 254                        CONFIG_SYS_PCI2_MEM_SIZE,
 255                        PCI_REGION_MEM);
 256
 257         /* outbound io */
 258         pci_set_region(r++,
 259                        CONFIG_SYS_PCI2_IO_BASE,
 260                        CONFIG_SYS_PCI2_IO_PHYS,
 261                        CONFIG_SYS_PCI2_IO_SIZE,
 262                        PCI_REGION_IO);
 263
 264         hose->region_count = r - hose->regions;
 265
 266         hose->first_busno=first_free_busno;
 267         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 268
 269         fsl_pci_init(hose);
 270
 271         first_free_busno=hose->last_busno+1;
 272         printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
 273                 hose->first_busno,hose->last_busno);
 274 }
 275 #else
 276         puts("PCI-EXPRESS 2: Disabled\n");
 277 #endif /* CONFIG_PCI2 */
 278
 279 }
 280
 281
 282 #if defined(CONFIG_OF_BOARD_SETUP)
 283 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
 284                         struct pci_controller *hose);
 285
 286 void
 287 ft_board_setup(void *blob, bd_t *bd)
 288 {
 289         ft_cpu_setup(blob, bd);
 290
 291 #ifdef CONFIG_PCI1
 292         ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 293 #endif
 294 #ifdef CONFIG_PCI2
 295         ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
 296 #endif
 297 }
 298 #endif
 299
 300
 301 /*
 302  * get_board_sys_clk
 303  *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 304  */
 305
 306 unsigned long
 307 get_board_sys_clk(ulong dummy)
 308 {
 309         u8 i, go_bit, rd_clks;
 310         ulong val = 0;
 311
 312         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 313         go_bit &= 0x01;
 314
 315         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 316         rd_clks &= 0x1C;
 317
 318         /*
 319          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 320          * should we be using the AUX register. Remember, we also set the
 321          * GO bit to boot from the alternate bank on the on-board flash
 322          */
 323
 324         if (go_bit) {
 325                 if (rd_clks == 0x1c)
 326                         i = in8(PIXIS_BASE + PIXIS_AUX);
 327                 else
 328                         i = in8(PIXIS_BASE + PIXIS_SPD);
 329         } else {
 330                 i = in8(PIXIS_BASE + PIXIS_SPD);
 331         }
 332
 333         i &= 0x07;
 334
 335         switch (i) {
 336         case 0:
 337                 val = 33000000;
 338                 break;
 339         case 1:
 340                 val = 40000000;
 341                 break;
 342         case 2:
 343                 val = 50000000;
 344                 break;
 345         case 3:
 346                 val = 66000000;
 347                 break;
 348         case 4:
 349                 val = 83000000;
 350                 break;
 351         case 5:
 352                 val = 100000000;
 353                 break;
 354         case 6:
 355                 val = 134000000;
 356                 break;
 357         case 7:
 358                 val = 166000000;
 359                 break;
 360         }
 361
 362         return val;
 363 }
 364
 365 int board_eth_init(bd_t *bis)
 366 {
 367         /* Initialize TSECs */
 368         cpu_eth_init(bis);
 369         return pci_eth_init(bis);
 370 }