board/freescale/mx31pdk/mx31pdk.c

   1 /*
   2  *
   3  * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
   4  *
   5  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10
  11 #include <common.h>
  12 #include <netdev.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <watchdog.h>
  17 #include <power/pmic.h>
  18 #include <fsl_pmic.h>
  19 #include <errno.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #ifdef CONFIG_SPL_BUILD
  24 void board_init_f(ulong bootflag)
  25 {
  26         /*
  27          * copy ourselves from where we are running to where we were
  28          * linked at. Use ulong pointers as all addresses involved
  29          * are 4-byte-aligned.
  30          */
  31         ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
  32         asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
  33         asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
  34         asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
  35         asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
  36         for (dst = start_ptr; dst < end_ptr; dst++)
  37                 *dst = *(dst+(run_ptr-link_ptr));
  38         /*
  39          * branch to nand_boot's link-time address.
  40          */
  41         asm volatile("ldr pc, =nand_boot");
  42 }
  43 #endif
  44
  45 int dram_init(void)
  46 {
  47         /* dram_init must store complete ramsize in gd->ram_size */
  48         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  49                                 PHYS_SDRAM_1_SIZE);
  50         return 0;
  51 }
  52
  53 int board_early_init_f(void)
  54 {
  55         /* CS5: CPLD incl. network controller */
  56         static const struct mxc_weimcs cs5 = {
  57                 /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  58                 CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 24, 0,  4,  3),
  59                 /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  60                 CSCR_L(2,  2,   2,   5,  2,  0,  5,  2,  0,  0,   0,   1),
  61                 /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  62                 CSCR_A(2,   2,  2,  2,  0,  0,  2,  2,  0,  0,  0,  0,   0,  0)
  63         };
  64
  65         mxc_setup_weimcs(5, &cs5);
  66
  67         /* Setup UART1 and SPI2 pins */
  68         mx31_uart1_hw_init();
  69         mx31_spi2_hw_init();
  70
  71         return 0;
  72 }
  73
  74 int board_init(void)
  75 {
  76         /* adress of boot parameters */
  77         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  78
  79         return 0;
  80 }
  81
  82 int board_late_init(void)
  83 {
  84         u32 val;
  85         struct pmic *p;
  86         int ret;
  87
  88         ret = pmic_init(I2C_PMIC);
  89         if (ret)
  90                 return ret;
  91
  92         p = pmic_get("FSL_PMIC");
  93         if (!p)
  94                 return -ENODEV;
  95         /* Enable RTC battery */
  96         pmic_reg_read(p, REG_POWER_CTL0, &val);
  97         pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
  98         pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
  99 #ifdef CONFIG_HW_WATCHDOG
 100         hw_watchdog_init();
 101 #endif
 102         return 0;
 103 }
 104
 105 int checkboard(void)
 106 {
 107         printf("Board: MX31PDK\n");
 108         return 0;
 109 }
 110
 111 int board_eth_init(bd_t *bis)
 112 {
 113         int rc = 0;
 114 #ifdef CONFIG_SMC911X
 115         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 116 #endif
 117         return rc;
 118 }