board/freescale/mx31pdk/mx31pdk.c

   1 /*
   2  *
   3  * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
   4  *
   5  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26
  27 #include <common.h>
  28 #include <netdev.h>
  29 #include <asm/arch/clock.h>
  30 #include <asm/arch/imx-regs.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <watchdog.h>
  33 #include <power/pmic.h>
  34 #include <fsl_pmic.h>
  35 #include <errno.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #ifdef CONFIG_HW_WATCHDOG
  40 void hw_watchdog_reset(void)
  41 {
  42         mxc_hw_watchdog_reset();
  43 }
  44 #endif
  45
  46 int dram_init(void)
  47 {
  48         /* dram_init must store complete ramsize in gd->ram_size */
  49         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  50                                 PHYS_SDRAM_1_SIZE);
  51         return 0;
  52 }
  53
  54 int board_early_init_f(void)
  55 {
  56         /* CS5: CPLD incl. network controller */
  57         static const struct mxc_weimcs cs5 = {
  58                 /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  59                 CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 24, 0,  4,  3),
  60                 /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  61                 CSCR_L(2,  2,   2,   5,  2,  0,  5,  2,  0,  0,   0,   1),
  62                 /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  63                 CSCR_A(2,   2,  2,  2,  0,  0,  2,  2,  0,  0,  0,  0,   0,  0)
  64         };
  65
  66         mxc_setup_weimcs(5, &cs5);
  67
  68         /* Setup UART1 and SPI2 pins */
  69         mx31_uart1_hw_init();
  70         mx31_spi2_hw_init();
  71
  72         return 0;
  73 }
  74
  75 int board_init(void)
  76 {
  77         /* adress of boot parameters */
  78         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  79
  80         return 0;
  81 }
  82
  83 int board_late_init(void)
  84 {
  85         u32 val;
  86         struct pmic *p;
  87         int ret;
  88
  89         ret = pmic_init(I2C_PMIC);
  90         if (ret)
  91                 return ret;
  92
  93         p = pmic_get("FSL_PMIC");
  94         if (!p)
  95                 return -ENODEV;
  96         /* Enable RTC battery */
  97         pmic_reg_read(p, REG_POWER_CTL0, &val);
  98         pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
  99         pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
 100 #ifdef CONFIG_HW_WATCHDOG
 101         mxc_hw_watchdog_enable();
 102 #endif
 103         return 0;
 104 }
 105
 106 int checkboard(void)
 107 {
 108         printf("Board: MX31PDK\n");
 109         return 0;
 110 }
 111
 112 int board_eth_init(bd_t *bis)
 113 {
 114         int rc = 0;
 115 #ifdef CONFIG_SMC911X
 116         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 117 #endif
 118         return rc;
 119 }