2 * (C) Copyright 2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/iomux-mx53.h>
14 #include <linux/errno.h>
17 #include <fsl_esdhc.h>
20 #define ETHERNET_INT IMX_GPIO_NR(2, 31)
22 DECLARE_GLOBAL_DATA_PTR
;
28 size1
= get_ram_size((void *)PHYS_SDRAM_1
, PHYS_SDRAM_1_SIZE
);
29 size2
= get_ram_size((void *)PHYS_SDRAM_2
, PHYS_SDRAM_2_SIZE
);
31 gd
->ram_size
= size1
+ size2
;
35 int dram_init_banksize(void)
37 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
38 gd
->bd
->bi_dram
[0].size
= PHYS_SDRAM_1_SIZE
;
40 gd
->bd
->bi_dram
[1].start
= PHYS_SDRAM_2
;
41 gd
->bd
->bi_dram
[1].size
= PHYS_SDRAM_2_SIZE
;
46 #ifdef CONFIG_NAND_MXC
47 static void setup_iomux_nand(void)
49 static const iomux_v3_cfg_t nand_pads
[] = {
50 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0
,
52 NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1
,
54 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0
,
56 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE
,
58 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE
,
60 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B
,
62 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B
,
64 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B
,
66 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0
,
67 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
68 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1
,
69 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
70 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2
,
71 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
72 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3
,
73 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
74 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4
,
75 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
76 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5
,
77 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
78 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6
,
79 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
80 NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7
,
81 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
86 reg
= __raw_readl(M4IF_BASE_ADDR
+ 0xc);
87 reg
&= ~M4IF_GENP_WEIM_MM_MASK
;
88 __raw_writel(reg
, M4IF_BASE_ADDR
+ 0xc);
89 for (i
= 0x4; i
< 0x94; i
+= 0x18) {
90 reg
= __raw_readl(WEIM_BASE_ADDR
+ i
);
91 reg
&= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK
;
92 __raw_writel(reg
, WEIM_BASE_ADDR
+ i
);
95 imx_iomux_v3_setup_multiple_pads(nand_pads
, ARRAY_SIZE(nand_pads
));
98 static void setup_iomux_nand(void)
103 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
104 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
106 static void setup_iomux_uart(void)
108 static const iomux_v3_cfg_t uart_pads
[] = {
109 NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX
, UART_PAD_CTRL
),
110 NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX
, UART_PAD_CTRL
),
113 imx_iomux_v3_setup_multiple_pads(uart_pads
, ARRAY_SIZE(uart_pads
));
116 #ifdef CONFIG_FSL_ESDHC
117 struct fsl_esdhc_cfg esdhc_cfg
[2] = {
118 {MMC_SDHC1_BASE_ADDR
},
119 {MMC_SDHC2_BASE_ADDR
},
122 int board_mmc_getcd(struct mmc
*mmc
)
124 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
127 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1
);
128 gpio_direction_input(IMX_GPIO_NR(1, 1));
129 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4
);
130 gpio_direction_input(IMX_GPIO_NR(1, 4));
132 if (cfg
->esdhc_base
== MMC_SDHC1_BASE_ADDR
)
133 ret
= !gpio_get_value(IMX_GPIO_NR(1, 1));
135 ret
= !gpio_get_value(IMX_GPIO_NR(1, 4));
140 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
142 #define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
143 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
146 int board_mmc_init(bd_t
*bis
)
148 static const iomux_v3_cfg_t sd1_pads
[] = {
149 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD
, SD_CMD_PAD_CTRL
),
150 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK
, SD_CLK_PAD_CTRL
),
151 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0
, SD_PAD_CTRL
),
152 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1
, SD_PAD_CTRL
),
153 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2
, SD_PAD_CTRL
),
154 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3
, SD_PAD_CTRL
),
157 static const iomux_v3_cfg_t sd2_pads
[] = {
158 NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD
, SD_CMD_PAD_CTRL
),
159 NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK
, SD_CLK_PAD_CTRL
),
160 NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0
, SD_PAD_CTRL
),
161 NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1
, SD_PAD_CTRL
),
162 NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2
, SD_PAD_CTRL
),
163 NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3
, SD_PAD_CTRL
),
164 NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4
, SD_PAD_CTRL
),
165 NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5
, SD_PAD_CTRL
),
166 NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6
, SD_PAD_CTRL
),
167 NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7
, SD_PAD_CTRL
),
173 esdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
174 esdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
176 for (index
= 0; index
< CONFIG_SYS_FSL_ESDHC_NUM
; index
++) {
179 imx_iomux_v3_setup_multiple_pads(sd1_pads
,
180 ARRAY_SIZE(sd1_pads
));
183 imx_iomux_v3_setup_multiple_pads(sd2_pads
,
184 ARRAY_SIZE(sd2_pads
));
187 printf("Warning: you configured more ESDHC controller"
188 "(%d) as supported by the board(2)\n",
189 CONFIG_SYS_FSL_ESDHC_NUM
);
192 ret
= fsl_esdhc_initialize(bis
, &esdhc_cfg
[index
]);
201 static void weim_smc911x_iomux(void)
203 static const iomux_v3_cfg_t weim_smc911x_pads
[] = {
205 NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16
,
206 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
207 NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17
,
208 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
209 NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18
,
210 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
211 NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19
,
212 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
213 NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20
,
214 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
215 NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21
,
216 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
217 NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22
,
218 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
219 NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23
,
220 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
221 NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24
,
222 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
223 NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25
,
224 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
225 NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26
,
226 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
227 NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27
,
228 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
229 NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28
,
230 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
231 NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29
,
232 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
233 NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30
,
234 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
235 NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31
,
236 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
239 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0
,
240 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
241 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1
,
242 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
243 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2
,
244 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
245 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3
,
246 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
247 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4
,
248 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
249 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5
,
250 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
251 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6
,
252 PAD_CTL_PKE
| PAD_CTL_DSE_HIGH
),
254 /* other EIM signals for ethernet */
255 MX53_PAD_EIM_OE__EMI_WEIM_OE
,
256 MX53_PAD_EIM_RW__EMI_WEIM_RW
,
257 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1
,
260 /* ETHERNET_INT as GPIO2_31 */
261 imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31
);
262 gpio_direction_input(ETHERNET_INT
);
265 imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads
,
266 ARRAY_SIZE(weim_smc911x_pads
));
269 static void weim_cs1_settings(void)
271 struct weim
*weim_regs
= (struct weim
*)WEIM_BASE_ADDR
;
273 writel(MX53ARD_CS1GCR1
, &weim_regs
->cs1gcr1
);
274 writel(0x0, &weim_regs
->cs1gcr2
);
275 writel(MX53ARD_CS1RCR1
, &weim_regs
->cs1rcr1
);
276 writel(MX53ARD_CS1RCR2
, &weim_regs
->cs1rcr2
);
277 writel(MX53ARD_CS1WCR1
, &weim_regs
->cs1wcr1
);
278 writel(0x0, &weim_regs
->cs1wcr2
);
279 writel(0x0, &weim_regs
->wcr
);
281 set_chipselect_size(CS0_64M_CS1_64M
);
284 int board_early_init_f(void)
293 /* address of boot parameters */
294 gd
->bd
->bi_boot_params
= PHYS_SDRAM_1
+ 0x100;
299 int board_eth_init(bd_t
*bis
)
303 weim_smc911x_iomux();
306 #ifdef CONFIG_SMC911X
307 rc
= smc911x_initialize(0, CONFIG_SMC911X_BASE
);
314 puts("Board: MX53ARD\n");