2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/iomux-mx53.h>
15 #include <asm/arch/clock.h>
16 #include <asm/errno.h>
17 #include <asm/imx-common/mx5_video.h>
21 #include <fsl_esdhc.h>
23 #include <power/pmic.h>
24 #include <dialog_pmic.h>
27 #include <ipu_pixfmt.h>
29 #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
31 DECLARE_GLOBAL_DATA_PTR
;
33 static uint32_t mx53_dram_size
[2];
35 phys_size_t
get_effective_memsize(void)
38 * WARNING: We must override get_effective_memsize() function here
39 * to report only the size of the first DRAM bank. This is to make
40 * U-Boot relocator place U-Boot into valid memory, that is, at the
41 * end of the first DRAM bank. If we did not override this function
42 * like so, U-Boot would be placed at the address of the first DRAM
43 * bank + total DRAM size - sizeof(uboot), which in the setup where
44 * each DRAM bank contains 512MiB of DRAM would result in placing
45 * U-Boot into invalid memory area close to the end of the first
48 return mx53_dram_size
[0];
53 mx53_dram_size
[0] = get_ram_size((void *)PHYS_SDRAM_1
, 1 << 30);
54 mx53_dram_size
[1] = get_ram_size((void *)PHYS_SDRAM_2
, 1 << 30);
56 gd
->ram_size
= mx53_dram_size
[0] + mx53_dram_size
[1];
61 void dram_init_banksize(void)
63 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
64 gd
->bd
->bi_dram
[0].size
= mx53_dram_size
[0];
66 gd
->bd
->bi_dram
[1].start
= PHYS_SDRAM_2
;
67 gd
->bd
->bi_dram
[1].size
= mx53_dram_size
[1];
70 u32
get_board_rev(void)
72 struct iim_regs
*iim
= (struct iim_regs
*)IMX_IIM_BASE
;
73 struct fuse_bank
*bank
= &iim
->bank
[0];
74 struct fuse_bank0_regs
*fuse
=
75 (struct fuse_bank0_regs
*)bank
->fuse_regs
;
77 int rev
= readl(&fuse
->gp
[6]);
79 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
))
82 return (get_cpu_rev() & ~(0xF << 8)) | (rev
& 0xF) << 8;
85 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
86 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
88 static void setup_iomux_uart(void)
90 static const iomux_v3_cfg_t uart_pads
[] = {
91 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX
, UART_PAD_CTRL
),
92 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX
, UART_PAD_CTRL
),
95 imx_iomux_v3_setup_multiple_pads(uart_pads
, ARRAY_SIZE(uart_pads
));
98 #ifdef CONFIG_USB_EHCI_MX5
99 int board_ehci_hcd_init(int port
)
101 /* request VBUS power enable pin, GPIO7_8 */
102 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8
);
103 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
108 static void setup_iomux_fec(void)
110 static const iomux_v3_cfg_t fec_pads
[] = {
111 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO
, PAD_CTL_HYS
|
112 PAD_CTL_DSE_HIGH
| PAD_CTL_PUS_22K_UP
| PAD_CTL_ODE
),
113 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC
, PAD_CTL_DSE_HIGH
),
114 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1
,
115 PAD_CTL_HYS
| PAD_CTL_PKE
),
116 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0
,
117 PAD_CTL_HYS
| PAD_CTL_PKE
),
118 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1
, PAD_CTL_DSE_HIGH
),
119 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0
, PAD_CTL_DSE_HIGH
),
120 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN
, PAD_CTL_DSE_HIGH
),
121 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK
,
122 PAD_CTL_HYS
| PAD_CTL_PKE
),
123 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER
,
124 PAD_CTL_HYS
| PAD_CTL_PKE
),
125 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV
,
126 PAD_CTL_HYS
| PAD_CTL_PKE
),
129 imx_iomux_v3_setup_multiple_pads(fec_pads
, ARRAY_SIZE(fec_pads
));
132 #ifdef CONFIG_FSL_ESDHC
133 struct fsl_esdhc_cfg esdhc_cfg
[2] = {
134 {MMC_SDHC1_BASE_ADDR
},
135 {MMC_SDHC3_BASE_ADDR
},
138 int board_mmc_getcd(struct mmc
*mmc
)
140 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
143 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11
);
144 gpio_direction_input(IMX_GPIO_NR(3, 11));
145 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13
);
146 gpio_direction_input(IMX_GPIO_NR(3, 13));
148 if (cfg
->esdhc_base
== MMC_SDHC1_BASE_ADDR
)
149 ret
= !gpio_get_value(IMX_GPIO_NR(3, 13));
151 ret
= !gpio_get_value(IMX_GPIO_NR(3, 11));
156 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
158 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
161 int board_mmc_init(bd_t
*bis
)
163 static const iomux_v3_cfg_t sd1_pads
[] = {
164 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD
, SD_CMD_PAD_CTRL
),
165 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK
, SD_PAD_CTRL
),
166 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0
, SD_PAD_CTRL
),
167 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1
, SD_PAD_CTRL
),
168 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2
, SD_PAD_CTRL
),
169 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3
, SD_PAD_CTRL
),
170 MX53_PAD_EIM_DA13__GPIO3_13
,
173 static const iomux_v3_cfg_t sd2_pads
[] = {
174 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD
,
176 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK
, SD_PAD_CTRL
),
177 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0
, SD_PAD_CTRL
),
178 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1
, SD_PAD_CTRL
),
179 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2
, SD_PAD_CTRL
),
180 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3
, SD_PAD_CTRL
),
181 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4
, SD_PAD_CTRL
),
182 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5
, SD_PAD_CTRL
),
183 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6
, SD_PAD_CTRL
),
184 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7
, SD_PAD_CTRL
),
185 MX53_PAD_EIM_DA11__GPIO3_11
,
191 esdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
192 esdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
194 for (index
= 0; index
< CONFIG_SYS_FSL_ESDHC_NUM
; index
++) {
197 imx_iomux_v3_setup_multiple_pads(sd1_pads
,
198 ARRAY_SIZE(sd1_pads
));
201 imx_iomux_v3_setup_multiple_pads(sd2_pads
,
202 ARRAY_SIZE(sd2_pads
));
205 printf("Warning: you configured more ESDHC controller"
206 "(%d) as supported by the board(2)\n",
207 CONFIG_SYS_FSL_ESDHC_NUM
);
210 ret
= fsl_esdhc_initialize(bis
, &esdhc_cfg
[index
]);
219 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
220 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
222 static void setup_iomux_i2c(void)
224 static const iomux_v3_cfg_t i2c1_pads
[] = {
225 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA
, I2C_PAD_CTRL
),
226 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL
, I2C_PAD_CTRL
),
229 imx_iomux_v3_setup_multiple_pads(i2c1_pads
, ARRAY_SIZE(i2c1_pads
));
232 static int power_init(void)
238 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
)) {
239 ret
= pmic_dialog_init(I2C_PMIC
);
243 p
= pmic_get("DIALOG_PMIC");
247 setenv("fdt_file", "imx53-qsb.dtb");
249 /* Set VDDA to 1.25V */
250 val
= DA9052_BUCKCORE_BCOREEN
| DA_BUCKCORE_VBCORE_1_250V
;
251 ret
= pmic_reg_write(p
, DA9053_BUCKCORE_REG
, val
);
253 printf("Writing to BUCKCORE_REG failed: %d\n", ret
);
257 pmic_reg_read(p
, DA9053_SUPPLY_REG
, &val
);
258 val
|= DA9052_SUPPLY_VBCOREGO
;
259 ret
= pmic_reg_write(p
, DA9053_SUPPLY_REG
, val
);
261 printf("Writing to SUPPLY_REG failed: %d\n", ret
);
265 /* Set Vcc peripheral to 1.30V */
266 ret
= pmic_reg_write(p
, DA9053_BUCKPRO_REG
, 0x62);
268 printf("Writing to BUCKPRO_REG failed: %d\n", ret
);
272 ret
= pmic_reg_write(p
, DA9053_SUPPLY_REG
, 0x62);
274 printf("Writing to SUPPLY_REG failed: %d\n", ret
);
281 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR
)) {
282 ret
= pmic_init(I2C_0
);
286 p
= pmic_get("FSL_PMIC");
290 setenv("fdt_file", "imx53-qsrb.dtb");
292 /* Set VDDGP to 1.25V for 1GHz on SW1 */
293 pmic_reg_read(p
, REG_SW_0
, &val
);
294 val
= (val
& ~SWx_VOLT_MASK_MC34708
) | SWx_1_250V_MC34708
;
295 ret
= pmic_reg_write(p
, REG_SW_0
, val
);
297 printf("Writing to REG_SW_0 failed: %d\n", ret
);
301 /* Set VCC as 1.30V on SW2 */
302 pmic_reg_read(p
, REG_SW_1
, &val
);
303 val
= (val
& ~SWx_VOLT_MASK_MC34708
) | SWx_1_300V_MC34708
;
304 ret
= pmic_reg_write(p
, REG_SW_1
, val
);
306 printf("Writing to REG_SW_1 failed: %d\n", ret
);
310 /* Set global reset timer to 4s */
311 pmic_reg_read(p
, REG_POWER_CTL2
, &val
);
312 val
= (val
& ~TIMER_MASK_MC34708
) | TIMER_4S_MC34708
;
313 ret
= pmic_reg_write(p
, REG_POWER_CTL2
, val
);
315 printf("Writing to REG_POWER_CTL2 failed: %d\n", ret
);
319 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
320 pmic_reg_read(p
, REG_MODE_0
, &val
);
321 val
|= (VUSBSEL_MC34708
| VUSBEN_MC34708
);
322 ret
= pmic_reg_write(p
, REG_MODE_0
, val
);
324 printf("Writing to REG_MODE_0 failed: %d\n", ret
);
328 /* Set SWBST to 5V in auto mode */
330 ret
= pmic_reg_write(p
, SWBST_CTRL
, val
);
332 printf("Writing to SWBST_CTRL failed: %d\n", ret
);
342 static void clock_1GHz(void)
345 u32 ref_clk
= MXC_HCLK
;
347 * After increasing voltage to 1.25V, we can switch
348 * CPU clock to 1GHz and DDR to 400MHz safely
350 ret
= mxc_set_clock(ref_clk
, 1000, MXC_ARM_CLK
);
352 printf("CPU: Switch CPU clock to 1GHZ failed\n");
354 ret
= mxc_set_clock(ref_clk
, 400, MXC_PERIPH_CLK
);
355 ret
|= mxc_set_clock(ref_clk
, 400, MXC_DDR_CLK
);
357 printf("CPU: Switch DDR clock to 400MHz failed\n");
360 int board_early_init_f(void)
370 * Do not overwrite the console
371 * Use always serial for U-Boot console
373 int overwrite_console(void)
380 gd
->bd
->bi_boot_params
= PHYS_SDRAM_1
+ 0x100;
382 mxc_set_sata_internal_clock();
388 int board_late_init(void)
398 puts("Board: MX53 LOCO\n");