2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/iomux-mx53.h>
15 #include <asm/arch/clock.h>
16 #include <asm/errno.h>
17 #include <asm/imx-common/mx5_video.h>
21 #include <fsl_esdhc.h>
23 #include <power/pmic.h>
24 #include <dialog_pmic.h>
27 #include <ipu_pixfmt.h>
29 #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
31 DECLARE_GLOBAL_DATA_PTR
;
37 size1
= get_ram_size((void *)PHYS_SDRAM_1
, PHYS_SDRAM_1_SIZE
);
38 size2
= get_ram_size((void *)PHYS_SDRAM_2
, PHYS_SDRAM_2_SIZE
);
40 gd
->ram_size
= size1
+ size2
;
44 void dram_init_banksize(void)
46 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
47 gd
->bd
->bi_dram
[0].size
= PHYS_SDRAM_1_SIZE
;
49 gd
->bd
->bi_dram
[1].start
= PHYS_SDRAM_2
;
50 gd
->bd
->bi_dram
[1].size
= PHYS_SDRAM_2_SIZE
;
53 u32
get_board_rev(void)
55 struct iim_regs
*iim
= (struct iim_regs
*)IMX_IIM_BASE
;
56 struct fuse_bank
*bank
= &iim
->bank
[0];
57 struct fuse_bank0_regs
*fuse
=
58 (struct fuse_bank0_regs
*)bank
->fuse_regs
;
60 int rev
= readl(&fuse
->gp
[6]);
62 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
))
65 return (get_cpu_rev() & ~(0xF << 8)) | (rev
& 0xF) << 8;
68 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
69 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
71 static void setup_iomux_uart(void)
73 static const iomux_v3_cfg_t uart_pads
[] = {
74 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX
, UART_PAD_CTRL
),
75 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX
, UART_PAD_CTRL
),
78 imx_iomux_v3_setup_multiple_pads(uart_pads
, ARRAY_SIZE(uart_pads
));
81 #ifdef CONFIG_USB_EHCI_MX5
82 int board_ehci_hcd_init(int port
)
84 /* request VBUS power enable pin, GPIO7_8 */
85 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8
);
86 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
91 static void setup_iomux_fec(void)
93 static const iomux_v3_cfg_t fec_pads
[] = {
94 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO
, PAD_CTL_HYS
|
95 PAD_CTL_DSE_HIGH
| PAD_CTL_PUS_22K_UP
| PAD_CTL_ODE
),
96 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC
, PAD_CTL_DSE_HIGH
),
97 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1
,
98 PAD_CTL_HYS
| PAD_CTL_PKE
),
99 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0
,
100 PAD_CTL_HYS
| PAD_CTL_PKE
),
101 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1
, PAD_CTL_DSE_HIGH
),
102 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0
, PAD_CTL_DSE_HIGH
),
103 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN
, PAD_CTL_DSE_HIGH
),
104 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK
,
105 PAD_CTL_HYS
| PAD_CTL_PKE
),
106 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER
,
107 PAD_CTL_HYS
| PAD_CTL_PKE
),
108 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV
,
109 PAD_CTL_HYS
| PAD_CTL_PKE
),
112 imx_iomux_v3_setup_multiple_pads(fec_pads
, ARRAY_SIZE(fec_pads
));
115 #ifdef CONFIG_FSL_ESDHC
116 struct fsl_esdhc_cfg esdhc_cfg
[2] = {
117 {MMC_SDHC1_BASE_ADDR
},
118 {MMC_SDHC3_BASE_ADDR
},
121 int board_mmc_getcd(struct mmc
*mmc
)
123 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
126 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11
);
127 gpio_direction_input(IMX_GPIO_NR(3, 11));
128 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13
);
129 gpio_direction_input(IMX_GPIO_NR(3, 13));
131 if (cfg
->esdhc_base
== MMC_SDHC1_BASE_ADDR
)
132 ret
= !gpio_get_value(IMX_GPIO_NR(3, 13));
134 ret
= !gpio_get_value(IMX_GPIO_NR(3, 11));
139 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
141 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
144 int board_mmc_init(bd_t
*bis
)
146 static const iomux_v3_cfg_t sd1_pads
[] = {
147 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD
, SD_CMD_PAD_CTRL
),
148 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK
, SD_PAD_CTRL
),
149 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0
, SD_PAD_CTRL
),
150 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1
, SD_PAD_CTRL
),
151 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2
, SD_PAD_CTRL
),
152 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3
, SD_PAD_CTRL
),
153 MX53_PAD_EIM_DA13__GPIO3_13
,
156 static const iomux_v3_cfg_t sd2_pads
[] = {
157 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD
,
159 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK
, SD_PAD_CTRL
),
160 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0
, SD_PAD_CTRL
),
161 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1
, SD_PAD_CTRL
),
162 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2
, SD_PAD_CTRL
),
163 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3
, SD_PAD_CTRL
),
164 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4
, SD_PAD_CTRL
),
165 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5
, SD_PAD_CTRL
),
166 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6
, SD_PAD_CTRL
),
167 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7
, SD_PAD_CTRL
),
168 MX53_PAD_EIM_DA11__GPIO3_11
,
174 esdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
175 esdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
177 for (index
= 0; index
< CONFIG_SYS_FSL_ESDHC_NUM
; index
++) {
180 imx_iomux_v3_setup_multiple_pads(sd1_pads
,
181 ARRAY_SIZE(sd1_pads
));
184 imx_iomux_v3_setup_multiple_pads(sd2_pads
,
185 ARRAY_SIZE(sd2_pads
));
188 printf("Warning: you configured more ESDHC controller"
189 "(%d) as supported by the board(2)\n",
190 CONFIG_SYS_FSL_ESDHC_NUM
);
193 status
|= fsl_esdhc_initialize(bis
, &esdhc_cfg
[index
]);
200 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
201 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
203 static void setup_iomux_i2c(void)
205 static const iomux_v3_cfg_t i2c1_pads
[] = {
206 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA
, I2C_PAD_CTRL
),
207 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL
, I2C_PAD_CTRL
),
210 imx_iomux_v3_setup_multiple_pads(i2c1_pads
, ARRAY_SIZE(i2c1_pads
));
213 static int power_init(void)
219 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
)) {
220 ret
= pmic_dialog_init(I2C_PMIC
);
224 p
= pmic_get("DIALOG_PMIC");
228 /* Set VDDA to 1.25V */
229 val
= DA9052_BUCKCORE_BCOREEN
| DA_BUCKCORE_VBCORE_1_250V
;
230 ret
= pmic_reg_write(p
, DA9053_BUCKCORE_REG
, val
);
232 printf("Writing to BUCKCORE_REG failed: %d\n", ret
);
236 pmic_reg_read(p
, DA9053_SUPPLY_REG
, &val
);
237 val
|= DA9052_SUPPLY_VBCOREGO
;
238 ret
= pmic_reg_write(p
, DA9053_SUPPLY_REG
, val
);
240 printf("Writing to SUPPLY_REG failed: %d\n", ret
);
244 /* Set Vcc peripheral to 1.30V */
245 ret
= pmic_reg_write(p
, DA9053_BUCKPRO_REG
, 0x62);
247 printf("Writing to BUCKPRO_REG failed: %d\n", ret
);
251 ret
= pmic_reg_write(p
, DA9053_SUPPLY_REG
, 0x62);
253 printf("Writing to SUPPLY_REG failed: %d\n", ret
);
260 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR
)) {
261 ret
= pmic_init(I2C_PMIC
);
265 p
= pmic_get("FSL_PMIC");
269 /* Set VDDGP to 1.25V for 1GHz on SW1 */
270 pmic_reg_read(p
, REG_SW_0
, &val
);
271 val
= (val
& ~SWx_VOLT_MASK_MC34708
) | SWx_1_250V_MC34708
;
272 ret
= pmic_reg_write(p
, REG_SW_0
, val
);
274 printf("Writing to REG_SW_0 failed: %d\n", ret
);
278 /* Set VCC as 1.30V on SW2 */
279 pmic_reg_read(p
, REG_SW_1
, &val
);
280 val
= (val
& ~SWx_VOLT_MASK_MC34708
) | SWx_1_300V_MC34708
;
281 ret
= pmic_reg_write(p
, REG_SW_1
, val
);
283 printf("Writing to REG_SW_1 failed: %d\n", ret
);
287 /* Set global reset timer to 4s */
288 pmic_reg_read(p
, REG_POWER_CTL2
, &val
);
289 val
= (val
& ~TIMER_MASK_MC34708
) | TIMER_4S_MC34708
;
290 ret
= pmic_reg_write(p
, REG_POWER_CTL2
, val
);
292 printf("Writing to REG_POWER_CTL2 failed: %d\n", ret
);
296 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
297 pmic_reg_read(p
, REG_MODE_0
, &val
);
298 val
|= (VUSBSEL_MC34708
| VUSBEN_MC34708
);
299 ret
= pmic_reg_write(p
, REG_MODE_0
, val
);
301 printf("Writing to REG_MODE_0 failed: %d\n", ret
);
305 /* Set SWBST to 5V in auto mode */
307 ret
= pmic_reg_write(p
, SWBST_CTRL
, val
);
309 printf("Writing to SWBST_CTRL failed: %d\n", ret
);
319 static void clock_1GHz(void)
322 u32 ref_clk
= MXC_HCLK
;
324 * After increasing voltage to 1.25V, we can switch
325 * CPU clock to 1GHz and DDR to 400MHz safely
327 ret
= mxc_set_clock(ref_clk
, 1000, MXC_ARM_CLK
);
329 printf("CPU: Switch CPU clock to 1GHZ failed\n");
331 ret
= mxc_set_clock(ref_clk
, 400, MXC_PERIPH_CLK
);
332 ret
|= mxc_set_clock(ref_clk
, 400, MXC_DDR_CLK
);
334 printf("CPU: Switch DDR clock to 400MHz failed\n");
337 int board_early_init_f(void)
346 int print_cpuinfo(void)
350 cpurev
= get_cpu_rev();
351 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
352 (cpurev
& 0xFF000) >> 12,
353 (cpurev
& 0x000F0) >> 4,
354 (cpurev
& 0x0000F) >> 0,
355 mxc_get_clock(MXC_ARM_CLK
) / 1000000);
356 printf("Reset cause: %s\n", get_reset_cause());
361 * Do not overwrite the console
362 * Use always serial for U-Boot console
364 int overwrite_console(void)
371 gd
->bd
->bi_boot_params
= PHYS_SDRAM_1
+ 0x100;
373 mxc_set_sata_internal_clock();
379 int board_late_init(void)
390 puts("Board: MX53 LOCO\n");