board/freescale/mx6qsabresd/mx6qsabresd.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <common.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/arch/imx-regs.h>
  24 #include <asm/arch/iomux.h>
  25 #include <asm/arch/mx6q_pins.h>
  26 #include <asm/errno.h>
  27 #include <asm/gpio.h>
  28 #include <asm/imx-common/iomux-v3.h>
  29 #include <asm/imx-common/boot_mode.h>
  30 #include <mmc.h>
  31 #include <fsl_esdhc.h>
  32 #include <miiphy.h>
  33 #include <netdev.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
  38         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  39         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  42         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  43         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  46         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  47         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  48
  49 int dram_init(void)
  50 {
  51         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  52
  53         return 0;
  54 }
  55
  56 iomux_v3_cfg_t const uart1_pads[] = {
  57         MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  58         MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  59 };
  60
  61 iomux_v3_cfg_t const enet_pads[] = {
  62         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64         MX6_PAD_RGMII_TXC__ENET_RGMII_TXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65         MX6_PAD_RGMII_TD0__ENET_RGMII_TD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66         MX6_PAD_RGMII_TD1__ENET_RGMII_TD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67         MX6_PAD_RGMII_TD2__ENET_RGMII_TD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68         MX6_PAD_RGMII_TD3__ENET_RGMII_TD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71         MX6_PAD_RGMII_RXC__ENET_RGMII_RXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72         MX6_PAD_RGMII_RD0__ENET_RGMII_RD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73         MX6_PAD_RGMII_RD1__ENET_RGMII_RD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74         MX6_PAD_RGMII_RD2__ENET_RGMII_RD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75         MX6_PAD_RGMII_RD3__ENET_RGMII_RD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77         /* AR8031 PHY Reset */
  78         MX6_PAD_ENET_CRS_DV__GPIO_1_25          | MUX_PAD_CTRL(NO_PAD_CTRL),
  79 };
  80
  81 static void setup_iomux_enet(void)
  82 {
  83         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  84
  85         /* Reset AR8031 PHY */
  86         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
  87         udelay(500);
  88         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  89 }
  90
  91 iomux_v3_cfg_t const usdhc2_pads[] = {
  92         MX6_PAD_SD2_CLK__USDHC2_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_SD2_CMD__USDHC2_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         MX6_PAD_SD2_DAT0__USDHC2_DAT0   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX6_PAD_SD2_DAT1__USDHC2_DAT1   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_SD2_DAT2__USDHC2_DAT2   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD2_DAT3__USDHC2_DAT3   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_NANDF_D4__USDHC2_DAT4   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_NANDF_D5__USDHC2_DAT5   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_NANDF_D6__USDHC2_DAT6   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_NANDF_D7__USDHC2_DAT7   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_NANDF_D2__GPIO_2_2      | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 103 };
 104
 105 iomux_v3_cfg_t const usdhc3_pads[] = {
 106         MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 108         MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110         MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 111         MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 112         MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_NANDF_D0__GPIO_2_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 117 };
 118
 119 iomux_v3_cfg_t const usdhc4_pads[] = {
 120         MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130 };
 131
 132 static void setup_iomux_uart(void)
 133 {
 134         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 135 }
 136
 137 #ifdef CONFIG_FSL_ESDHC
 138 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 139         {USDHC2_BASE_ADDR},
 140         {USDHC3_BASE_ADDR},
 141         {USDHC4_BASE_ADDR},
 142 };
 143
 144 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 145 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 146
 147 int board_mmc_getcd(struct mmc *mmc)
 148 {
 149         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 150         int ret = 0;
 151
 152         switch (cfg->esdhc_base) {
 153         case USDHC2_BASE_ADDR:
 154                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 155                 break;
 156         case USDHC3_BASE_ADDR:
 157                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 158                 break;
 159         case USDHC4_BASE_ADDR:
 160                 ret = 1; /* eMMC/uSDHC4 is always present */
 161                 break;
 162         }
 163
 164         return ret;
 165 }
 166
 167 int board_mmc_init(bd_t *bis)
 168 {
 169         int i;
 170
 171         /*
 172          * According to the board_mmc_init() the following map is done:
 173          * (U-boot device node)    (Physical Port)
 174          * mmc0                    SD2
 175          * mmc1                    SD3
 176          * mmc2                    eMMC
 177          */
 178         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 179                 switch (i) {
 180                 case 0:
 181                         imx_iomux_v3_setup_multiple_pads(
 182                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 183                         gpio_direction_input(USDHC2_CD_GPIO);
 184                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 185                         break;
 186                 case 1:
 187                         imx_iomux_v3_setup_multiple_pads(
 188                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 189                         gpio_direction_input(USDHC3_CD_GPIO);
 190                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 191                         break;
 192                 case 2:
 193                         imx_iomux_v3_setup_multiple_pads(
 194                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 195                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 196                         break;
 197                 default:
 198                         printf("Warning: you configured more USDHC controllers"
 199                                 "(%d) than supported by the board\n", i + 1);
 200                         return 0;
 201                }
 202
 203                if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
 204                         printf("Warning: failed to initialize mmc dev %d\n", i);
 205         }
 206
 207         return 0;
 208 }
 209 #endif
 210
 211 int mx6_rgmii_rework(struct phy_device *phydev)
 212 {
 213         unsigned short val;
 214
 215         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 216         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 217         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 218         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 219
 220         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 221         val &= 0xffe3;
 222         val |= 0x18;
 223         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 224
 225         /* introduce tx clock delay */
 226         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 227         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 228         val |= 0x0100;
 229         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 230
 231         return 0;
 232 }
 233
 234 int board_phy_config(struct phy_device *phydev)
 235 {
 236         mx6_rgmii_rework(phydev);
 237
 238         if (phydev->drv->config)
 239                 phydev->drv->config(phydev);
 240
 241         return 0;
 242 }
 243
 244 int board_eth_init(bd_t *bis)
 245 {
 246         int ret;
 247
 248         setup_iomux_enet();
 249
 250         ret = cpu_eth_init(bis);
 251         if (ret)
 252                 printf("FEC MXC: %s:failed\n", __func__);
 253
 254         return 0;
 255 }
 256
 257 int board_early_init_f(void)
 258 {
 259         setup_iomux_uart();
 260
 261         return 0;
 262 }
 263
 264 int board_init(void)
 265 {
 266         /* address of boot parameters */
 267         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 268
 269         return 0;
 270 }
 271
 272 #ifdef CONFIG_CMD_BMODE
 273 static const struct boot_mode board_boot_modes[] = {
 274         /* 4 bit bus width */
 275         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 276         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 277         /* 8 bit bus width */
 278         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 279         {NULL,   0},
 280 };
 281 #endif
 282
 283 int board_late_init(void)
 284 {
 285 #ifdef CONFIG_CMD_BMODE
 286         add_board_boot_modes(board_boot_modes);
 287 #endif
 288
 289         return 0;
 290 }
 291
 292 int checkboard(void)
 293 {
 294         puts("Board: MX6Q-SabreSD\n");
 295
 296         return 0;
 297 }