board/freescale/mx6slevk/mx6slevk.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/iomux-v3.h>
  16 #include <asm/io.h>
  17 #include <linux/sizes.h>
  18 #include <common.h>
  19 #include <fsl_esdhc.h>
  20 #include <mmc.h>
  21 #include <netdev.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  26         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  27         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  28
  29 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |                    \
  30         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  31         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  32
  33 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  34         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  35         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  36
  37 #define ETH_PHY_RESET   IMX_GPIO_NR(4, 21)
  38
  39 int dram_init(void)
  40 {
  41         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  42
  43         return 0;
  44 }
  45
  46 static iomux_v3_cfg_t const uart1_pads[] = {
  47         MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  48         MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  49 };
  50
  51 static iomux_v3_cfg_t const usdhc2_pads[] = {
  52         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  53         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  54         MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  55         MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  56         MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  57         MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  58 };
  59
  60 static iomux_v3_cfg_t const fec_pads[] = {
  61         MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62         MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63         MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64         MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65         MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66         MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67         MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68         MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69         MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70         MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  71         MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  72 };
  73
  74 static void setup_iomux_uart(void)
  75 {
  76         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  77 }
  78
  79 static void setup_iomux_fec(void)
  80 {
  81         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  82
  83         /* Reset LAN8720 PHY */
  84         gpio_direction_output(ETH_PHY_RESET , 0);
  85         udelay(1000);
  86         gpio_set_value(ETH_PHY_RESET, 1);
  87 }
  88
  89 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  90         {USDHC2_BASE_ADDR},
  91 };
  92
  93 int board_mmc_getcd(struct mmc *mmc)
  94 {
  95         return 1;       /* Assume boot SD always present */
  96 }
  97
  98 int board_mmc_init(bd_t *bis)
  99 {
 100         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 101
 102         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 103         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 104 }
 105
 106 #ifdef CONFIG_FEC_MXC
 107 int board_eth_init(bd_t *bis)
 108 {
 109         setup_iomux_fec();
 110
 111         return cpu_eth_init(bis);
 112 }
 113
 114 static int setup_fec(void)
 115 {
 116         struct iomuxc_base_regs *iomuxc_regs =
 117                                 (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
 118         int ret;
 119
 120         /* clear gpr1[14], gpr1[18:17] to select anatop clock */
 121         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 122
 123         ret = enable_fec_anatop_clock(ENET_50MHz);
 124         if (ret)
 125                 return ret;
 126
 127         return 0;
 128 }
 129 #endif
 130
 131
 132 int board_early_init_f(void)
 133 {
 134         setup_iomux_uart();
 135         return 0;
 136 }
 137
 138 int board_init(void)
 139 {
 140         /* address of boot parameters */
 141         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 142
 143 #ifdef  CONFIG_FEC_MXC
 144         setup_fec();
 145 #endif
 146         return 0;
 147 }
 148
 149 u32 get_board_rev(void)
 150 {
 151         return get_cpu_rev();
 152 }
 153
 154 int checkboard(void)
 155 {
 156         puts("Board: MX6SLEVK\n");
 157
 158         return 0;
 159 }