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Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging
[people/ms/u-boot.git] / board / freescale / mx6ul_14x14_evk / mx6ul_14x14_evk.c
1 /*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6ul_pins.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/gpio.h>
15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/mxc_i2c.h>
18 #include <asm/io.h>
19 #include <common.h>
20 #include <fsl_esdhc.h>
21 #include <i2c.h>
22 #include <miiphy.h>
23 #include <linux/sizes.h>
24 #include <mmc.h>
25 #include <netdev.h>
26 #include <power/pmic.h>
27 #include <power/pfuze3000_pmic.h>
28 #include "../common/pfuze.h"
29 #include <usb.h>
30 #include <usb/ehci-fsl.h>
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37
38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41
42 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
43 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
44 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
46 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
49 PAD_CTL_ODE)
50
51 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
52 PAD_CTL_SPEED_HIGH | \
53 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
54
55 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
56 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
57
58 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
59 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
60
61 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62
63 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
64 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
65
66 #define IOX_SDI IMX_GPIO_NR(5, 10)
67 #define IOX_STCP IMX_GPIO_NR(5, 7)
68 #define IOX_SHCP IMX_GPIO_NR(5, 11)
69 #define IOX_OE IMX_GPIO_NR(5, 18)
70
71 static iomux_v3_cfg_t const iox_pads[] = {
72 /* IOX_SDI */
73 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
74 /* IOX_SHCP */
75 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
76 /* IOX_STCP */
77 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
78 /* IOX_nOE */
79 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
80 };
81
82 /*
83 * HDMI_nRST --> Q0
84 * ENET1_nRST --> Q1
85 * ENET2_nRST --> Q2
86 * CAN1_2_STBY --> Q3
87 * BT_nPWD --> Q4
88 * CSI_RST --> Q5
89 * CSI_PWDN --> Q6
90 * LCD_nPWREN --> Q7
91 */
92 enum qn {
93 HDMI_NRST,
94 ENET1_NRST,
95 ENET2_NRST,
96 CAN1_2_STBY,
97 BT_NPWD,
98 CSI_RST,
99 CSI_PWDN,
100 LCD_NPWREN,
101 };
102
103 enum qn_func {
104 qn_reset,
105 qn_enable,
106 qn_disable,
107 };
108
109 enum qn_level {
110 qn_low = 0,
111 qn_high = 1,
112 };
113
114 static enum qn_level seq[3][2] = {
115 {0, 1}, {1, 1}, {0, 0}
116 };
117
118 static enum qn_func qn_output[8] = {
119 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
120 qn_disable, qn_enable
121 };
122
123 static void iox74lv_init(void)
124 {
125 int i;
126
127 gpio_direction_output(IOX_OE, 0);
128
129 for (i = 7; i >= 0; i--) {
130 gpio_direction_output(IOX_SHCP, 0);
131 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
132 udelay(500);
133 gpio_direction_output(IOX_SHCP, 1);
134 udelay(500);
135 }
136
137 gpio_direction_output(IOX_STCP, 0);
138 udelay(500);
139 /*
140 * shift register will be output to pins
141 */
142 gpio_direction_output(IOX_STCP, 1);
143
144 for (i = 7; i >= 0; i--) {
145 gpio_direction_output(IOX_SHCP, 0);
146 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
147 udelay(500);
148 gpio_direction_output(IOX_SHCP, 1);
149 udelay(500);
150 }
151 gpio_direction_output(IOX_STCP, 0);
152 udelay(500);
153 /*
154 * shift register will be output to pins
155 */
156 gpio_direction_output(IOX_STCP, 1);
157
158 gpio_direction_output(IOX_OE, 1);
159 };
160
161 #ifdef CONFIG_SYS_I2C_MXC
162 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
163 /* I2C1 for PMIC and EEPROM */
164 static struct i2c_pads_info i2c_pad_info1 = {
165 .scl = {
166 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
167 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
168 .gp = IMX_GPIO_NR(1, 28),
169 },
170 .sda = {
171 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
172 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
173 .gp = IMX_GPIO_NR(1, 29),
174 },
175 };
176
177 #ifdef CONFIG_POWER
178 #define I2C_PMIC 0
179 int power_init_board(void)
180 {
181 if (is_mx6ul_9x9_evk()) {
182 struct pmic *pfuze;
183 int ret;
184 unsigned int reg, rev_id;
185
186 ret = power_pfuze3000_init(I2C_PMIC);
187 if (ret)
188 return ret;
189
190 pfuze = pmic_get("PFUZE3000");
191 ret = pmic_probe(pfuze);
192 if (ret)
193 return ret;
194
195 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
196 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
197 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
198 reg, rev_id);
199
200 /* disable Low Power Mode during standby mode */
201 pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
202 reg |= 0x1;
203 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
204
205 /* SW1B step ramp up time from 2us to 4us/25mV */
206 reg = 0x40;
207 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
208
209 /* SW1B mode to APS/PFM */
210 reg = 0xc;
211 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
212
213 /* SW1B standby voltage set to 0.975V */
214 reg = 0xb;
215 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
216 }
217
218 return 0;
219 }
220 #endif
221 #endif
222
223 int dram_init(void)
224 {
225 gd->ram_size = imx_ddr_size();
226
227 return 0;
228 }
229
230 static iomux_v3_cfg_t const uart1_pads[] = {
231 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
232 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
233 };
234
235 static iomux_v3_cfg_t const usdhc1_pads[] = {
236 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
237 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
238 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
239 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
240 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
241 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
242
243 /* VSELECT */
244 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
245 /* CD */
246 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
247 /* RST_B */
248 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
249 };
250
251 /*
252 * mx6ul_14x14_evk board default supports sd card. If want to use
253 * EMMC, need to do board rework for sd2.
254 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
255 * emmc, need to define this macro.
256 */
257 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
258 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
259 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
260 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
261 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
262 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
263 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
264 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
265 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
266 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
267 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
268 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
269
270 /*
271 * RST_B
272 */
273 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
274 };
275 #else
276 static iomux_v3_cfg_t const usdhc2_pads[] = {
277 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
278 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
279 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
280 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
281 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
282 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
283 };
284
285 static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
286 /*
287 * The evk board uses DAT3 to detect CD card plugin,
288 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
289 */
290 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
291 };
292
293 static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
294 MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
295 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
296 };
297 #endif
298
299 static void setup_iomux_uart(void)
300 {
301 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
302 }
303
304 #ifdef CONFIG_FSL_QSPI
305
306 #define QSPI_PAD_CTRL1 \
307 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
308 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
309
310 static iomux_v3_cfg_t const quadspi_pads[] = {
311 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
312 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
313 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
314 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
315 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
316 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
317 };
318
319 static int board_qspi_init(void)
320 {
321 /* Set the iomux */
322 imx_iomux_v3_setup_multiple_pads(quadspi_pads,
323 ARRAY_SIZE(quadspi_pads));
324 /* Set the clock */
325 enable_qspi_clk(0);
326
327 return 0;
328 }
329 #endif
330
331 #ifdef CONFIG_FSL_ESDHC
332 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
333 {USDHC1_BASE_ADDR, 0, 4},
334 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
335 {USDHC2_BASE_ADDR, 0, 8},
336 #else
337 {USDHC2_BASE_ADDR, 0, 4},
338 #endif
339 };
340
341 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
342 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
343 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
344 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
345
346 int board_mmc_getcd(struct mmc *mmc)
347 {
348 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
349 int ret = 0;
350
351 switch (cfg->esdhc_base) {
352 case USDHC1_BASE_ADDR:
353 ret = !gpio_get_value(USDHC1_CD_GPIO);
354 break;
355 case USDHC2_BASE_ADDR:
356 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
357 ret = 1;
358 #else
359 imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
360 ARRAY_SIZE(usdhc2_cd_pads));
361 gpio_direction_input(USDHC2_CD_GPIO);
362
363 /*
364 * Since it is the DAT3 pin, this pin is pulled to
365 * low voltage if no card
366 */
367 ret = gpio_get_value(USDHC2_CD_GPIO);
368
369 imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
370 ARRAY_SIZE(usdhc2_dat3_pads));
371 #endif
372 break;
373 }
374
375 return ret;
376 }
377
378 int board_mmc_init(bd_t *bis)
379 {
380 #ifdef CONFIG_SPL_BUILD
381 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
382 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
383 ARRAY_SIZE(usdhc2_emmc_pads));
384 #else
385 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
386 #endif
387 gpio_direction_output(USDHC2_PWR_GPIO, 0);
388 udelay(500);
389 gpio_direction_output(USDHC2_PWR_GPIO, 1);
390 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
391 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
392 #else
393 int i, ret;
394
395 /*
396 * According to the board_mmc_init() the following map is done:
397 * (U-Boot device node) (Physical Port)
398 * mmc0 USDHC1
399 * mmc1 USDHC2
400 */
401 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
402 switch (i) {
403 case 0:
404 imx_iomux_v3_setup_multiple_pads(
405 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
406 gpio_direction_input(USDHC1_CD_GPIO);
407 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
408
409 gpio_direction_output(USDHC1_PWR_GPIO, 0);
410 udelay(500);
411 gpio_direction_output(USDHC1_PWR_GPIO, 1);
412 break;
413 case 1:
414 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
415 imx_iomux_v3_setup_multiple_pads(
416 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
417 #else
418 imx_iomux_v3_setup_multiple_pads(
419 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
420 #endif
421 gpio_direction_output(USDHC2_PWR_GPIO, 0);
422 udelay(500);
423 gpio_direction_output(USDHC2_PWR_GPIO, 1);
424 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
425 break;
426 default:
427 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
428 return -EINVAL;
429 }
430
431 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
432 if (ret) {
433 printf("Warning: failed to initialize mmc dev %d\n", i);
434 return ret;
435 }
436 }
437 #endif
438 return 0;
439 }
440 #endif
441
442 #ifdef CONFIG_USB_EHCI_MX6
443 #define USB_OTHERREGS_OFFSET 0x800
444 #define UCTRL_PWR_POL (1 << 9)
445
446 static iomux_v3_cfg_t const usb_otg_pads[] = {
447 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
448 };
449
450 /* At default the 3v3 enables the MIC2026 for VBUS power */
451 static void setup_usb(void)
452 {
453 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
454 ARRAY_SIZE(usb_otg_pads));
455 }
456
457 int board_usb_phy_mode(int port)
458 {
459 if (port == 1)
460 return USB_INIT_HOST;
461 else
462 return usb_phy_mode(port);
463 }
464
465 int board_ehci_hcd_init(int port)
466 {
467 u32 *usbnc_usb_ctrl;
468
469 if (port > 1)
470 return -EINVAL;
471
472 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
473 port * 4);
474
475 /* Set Power polarity */
476 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
477
478 return 0;
479 }
480 #endif
481
482 #ifdef CONFIG_FEC_MXC
483 /*
484 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
485 * be used for ENET1 or ENET2, cannot be used for both.
486 */
487 static iomux_v3_cfg_t const fec1_pads[] = {
488 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
489 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
490 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
491 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
492 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
493 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
494 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
495 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
496 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
497 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
498 };
499
500 static iomux_v3_cfg_t const fec2_pads[] = {
501 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
502 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
503
504 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
505 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
506 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
507 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
508
509 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
510 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
511 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
512 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
513 };
514
515 static void setup_iomux_fec(int fec_id)
516 {
517 if (fec_id == 0)
518 imx_iomux_v3_setup_multiple_pads(fec1_pads,
519 ARRAY_SIZE(fec1_pads));
520 else
521 imx_iomux_v3_setup_multiple_pads(fec2_pads,
522 ARRAY_SIZE(fec2_pads));
523 }
524
525 int board_eth_init(bd_t *bis)
526 {
527 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
528
529 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
530 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
531 }
532
533 static int setup_fec(int fec_id)
534 {
535 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
536 int ret;
537
538 if (fec_id == 0) {
539 /*
540 * Use 50M anatop loopback REF_CLK1 for ENET1,
541 * clear gpr1[13], set gpr1[17].
542 */
543 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
544 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
545 } else {
546 /*
547 * Use 50M anatop loopback REF_CLK2 for ENET2,
548 * clear gpr1[14], set gpr1[18].
549 */
550 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
551 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
552 }
553
554 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
555 if (ret)
556 return ret;
557
558 enable_enet_clk(1);
559
560 return 0;
561 }
562
563 int board_phy_config(struct phy_device *phydev)
564 {
565 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
566
567 if (phydev->drv->config)
568 phydev->drv->config(phydev);
569
570 return 0;
571 }
572 #endif
573
574 #ifdef CONFIG_VIDEO_MXS
575 static iomux_v3_cfg_t const lcd_pads[] = {
576 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
577 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
578 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
579 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
580 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
581 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
582 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
583 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
584 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
585 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
586 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
587 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
588 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
589 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
590 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
591 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
592 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
593 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
594 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
595 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
596 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
597 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
598 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
599 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
600 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
601 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
602 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
603 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
604
605 /* LCD_RST */
606 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
607
608 /* Use GPIO for Brightness adjustment, duty cycle = period. */
609 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
610 };
611
612 static int setup_lcd(void)
613 {
614 enable_lcdif_clock(LCDIF1_BASE_ADDR);
615
616 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
617
618 /* Reset the LCD */
619 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
620 udelay(500);
621 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
622
623 /* Set Brightness to high */
624 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
625
626 return 0;
627 }
628 #endif
629
630 int board_early_init_f(void)
631 {
632 setup_iomux_uart();
633
634 return 0;
635 }
636
637 int board_init(void)
638 {
639 /* Address of boot parameters */
640 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
641
642 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
643
644 iox74lv_init();
645
646 #ifdef CONFIG_SYS_I2C_MXC
647 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
648 #endif
649
650 #ifdef CONFIG_FEC_MXC
651 setup_fec(CONFIG_FEC_ENET_DEV);
652 #endif
653
654 #ifdef CONFIG_USB_EHCI_MX6
655 setup_usb();
656 #endif
657
658 #ifdef CONFIG_FSL_QSPI
659 board_qspi_init();
660 #endif
661
662 #ifdef CONFIG_VIDEO_MXS
663 setup_lcd();
664 #endif
665
666 return 0;
667 }
668
669 #ifdef CONFIG_CMD_BMODE
670 static const struct boot_mode board_boot_modes[] = {
671 /* 4 bit bus width */
672 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
673 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
674 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
675 {NULL, 0},
676 };
677 #endif
678
679 int board_late_init(void)
680 {
681 #ifdef CONFIG_CMD_BMODE
682 add_board_boot_modes(board_boot_modes);
683 #endif
684
685 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
686 setenv("board_name", "EVK");
687
688 if (is_mx6ul_9x9_evk())
689 setenv("board_rev", "9X9");
690 else
691 setenv("board_rev", "14X14");
692 #endif
693
694 return 0;
695 }
696
697 int checkboard(void)
698 {
699 if (is_mx6ul_9x9_evk())
700 puts("Board: MX6UL 9x9 EVK\n");
701 else
702 puts("Board: MX6UL 14x14 EVK\n");
703
704 return 0;
705 }
706
707 #ifdef CONFIG_SPL_BUILD
708 #include <libfdt.h>
709 #include <spl.h>
710 #include <asm/arch/mx6-ddr.h>
711
712
713 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
714 .grp_addds = 0x00000030,
715 .grp_ddrmode_ctl = 0x00020000,
716 .grp_b0ds = 0x00000030,
717 .grp_ctlds = 0x00000030,
718 .grp_b1ds = 0x00000030,
719 .grp_ddrpke = 0x00000000,
720 .grp_ddrmode = 0x00020000,
721 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
722 .grp_ddr_type = 0x00080000,
723 #else
724 .grp_ddr_type = 0x000c0000,
725 #endif
726 };
727
728 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
729 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
730 .dram_dqm0 = 0x00000030,
731 .dram_dqm1 = 0x00000030,
732 .dram_ras = 0x00000030,
733 .dram_cas = 0x00000030,
734 .dram_odt0 = 0x00000000,
735 .dram_odt1 = 0x00000000,
736 .dram_sdba2 = 0x00000000,
737 .dram_sdclk_0 = 0x00000030,
738 .dram_sdqs0 = 0x00003030,
739 .dram_sdqs1 = 0x00003030,
740 .dram_reset = 0x00000030,
741 };
742
743 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
744 .p0_mpwldectrl0 = 0x00000000,
745 .p0_mpdgctrl0 = 0x20000000,
746 .p0_mprddlctl = 0x4040484f,
747 .p0_mpwrdlctl = 0x40405247,
748 .mpzqlp2ctl = 0x1b4700c7,
749 };
750
751 static struct mx6_lpddr2_cfg mem_ddr = {
752 .mem_speed = 800,
753 .density = 2,
754 .width = 16,
755 .banks = 4,
756 .rowaddr = 14,
757 .coladdr = 10,
758 .trcd_lp = 1500,
759 .trppb_lp = 1500,
760 .trpab_lp = 2000,
761 .trasmin = 4250,
762 };
763
764 struct mx6_ddr_sysinfo ddr_sysinfo = {
765 .dsize = 0,
766 .cs_density = 18,
767 .ncs = 1,
768 .cs1_mirror = 0,
769 .walat = 0,
770 .ralat = 5,
771 .mif3_mode = 3,
772 .bi_on = 1,
773 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
774 .rtt_nom = 0,
775 .sde_to_rst = 0, /* LPDDR2 does not need this field */
776 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
777 .ddr_type = DDR_TYPE_LPDDR2,
778 };
779
780 #else
781 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
782 .dram_dqm0 = 0x00000030,
783 .dram_dqm1 = 0x00000030,
784 .dram_ras = 0x00000030,
785 .dram_cas = 0x00000030,
786 .dram_odt0 = 0x00000030,
787 .dram_odt1 = 0x00000030,
788 .dram_sdba2 = 0x00000000,
789 .dram_sdclk_0 = 0x00000008,
790 .dram_sdqs0 = 0x00000038,
791 .dram_sdqs1 = 0x00000030,
792 .dram_reset = 0x00000030,
793 };
794
795 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
796 .p0_mpwldectrl0 = 0x00070007,
797 .p0_mpdgctrl0 = 0x41490145,
798 .p0_mprddlctl = 0x40404546,
799 .p0_mpwrdlctl = 0x4040524D,
800 };
801
802 struct mx6_ddr_sysinfo ddr_sysinfo = {
803 .dsize = 0,
804 .cs_density = 20,
805 .ncs = 1,
806 .cs1_mirror = 0,
807 .rtt_wr = 2,
808 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
809 .walat = 1, /* Write additional latency */
810 .ralat = 5, /* Read additional latency */
811 .mif3_mode = 3, /* Command prediction working mode */
812 .bi_on = 1, /* Bank interleaving enabled */
813 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
814 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
815 .ddr_type = DDR_TYPE_DDR3,
816 };
817
818 static struct mx6_ddr3_cfg mem_ddr = {
819 .mem_speed = 800,
820 .density = 4,
821 .width = 16,
822 .banks = 8,
823 .rowaddr = 15,
824 .coladdr = 10,
825 .pagesz = 2,
826 .trcd = 1375,
827 .trcmin = 4875,
828 .trasmin = 3500,
829 };
830 #endif
831
832 static void ccgr_init(void)
833 {
834 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
835
836 writel(0xFFFFFFFF, &ccm->CCGR0);
837 writel(0xFFFFFFFF, &ccm->CCGR1);
838 writel(0xFFFFFFFF, &ccm->CCGR2);
839 writel(0xFFFFFFFF, &ccm->CCGR3);
840 writel(0xFFFFFFFF, &ccm->CCGR4);
841 writel(0xFFFFFFFF, &ccm->CCGR5);
842 writel(0xFFFFFFFF, &ccm->CCGR6);
843 writel(0xFFFFFFFF, &ccm->CCGR7);
844 }
845
846 static void spl_dram_init(void)
847 {
848 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
849 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
850 }
851
852 void board_init_f(ulong dummy)
853 {
854 /* setup AIPS and disable watchdog */
855 arch_cpu_init();
856
857 ccgr_init();
858
859 /* iomux and setup of i2c */
860 board_early_init_f();
861
862 /* setup GP timer */
863 timer_init();
864
865 /* UART clocks enabled and gd valid - init serial console */
866 preloader_console_init();
867
868 /* DDR initialization */
869 spl_dram_init();
870
871 /* Clear the BSS. */
872 memset(__bss_start, 0, __bss_end - __bss_start);
873
874 /* load/boot image from boot device */
875 board_init_r(NULL, 0);
876 }
877 #endif
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