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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
[people/ms/u-boot.git] / board / freescale / mx6ul_14x14_evk / mx6ul_14x14_evk.c
1 /*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6ul_pins.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/gpio.h>
15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/mxc_i2c.h>
18 #include <asm/io.h>
19 #include <common.h>
20 #include <fsl_esdhc.h>
21 #include <i2c.h>
22 #include <miiphy.h>
23 #include <linux/sizes.h>
24 #include <mmc.h>
25 #include <netdev.h>
26 #include <usb.h>
27 #include <usb/ehci-fsl.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
33 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
34
35 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
36 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38
39 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
44 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
45 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
46 PAD_CTL_ODE)
47
48 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
49 PAD_CTL_SPEED_HIGH | \
50 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
51
52 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
53 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
54
55 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
56
57 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
58 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
59
60 #define IOX_SDI IMX_GPIO_NR(5, 10)
61 #define IOX_STCP IMX_GPIO_NR(5, 7)
62 #define IOX_SHCP IMX_GPIO_NR(5, 11)
63 #define IOX_OE IMX_GPIO_NR(5, 18)
64
65 static iomux_v3_cfg_t const iox_pads[] = {
66 /* IOX_SDI */
67 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
68 /* IOX_SHCP */
69 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
70 /* IOX_STCP */
71 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
72 /* IOX_nOE */
73 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
74 };
75
76 /*
77 * HDMI_nRST --> Q0
78 * ENET1_nRST --> Q1
79 * ENET2_nRST --> Q2
80 * CAN1_2_STBY --> Q3
81 * BT_nPWD --> Q4
82 * CSI_RST --> Q5
83 * CSI_PWDN --> Q6
84 * LCD_nPWREN --> Q7
85 */
86 enum qn {
87 HDMI_NRST,
88 ENET1_NRST,
89 ENET2_NRST,
90 CAN1_2_STBY,
91 BT_NPWD,
92 CSI_RST,
93 CSI_PWDN,
94 LCD_NPWREN,
95 };
96
97 enum qn_func {
98 qn_reset,
99 qn_enable,
100 qn_disable,
101 };
102
103 enum qn_level {
104 qn_low = 0,
105 qn_high = 1,
106 };
107
108 static enum qn_level seq[3][2] = {
109 {0, 1}, {1, 1}, {0, 0}
110 };
111
112 static enum qn_func qn_output[8] = {
113 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
114 qn_disable, qn_enable
115 };
116
117 static void iox74lv_init(void)
118 {
119 int i;
120
121 gpio_direction_output(IOX_OE, 0);
122
123 for (i = 7; i >= 0; i--) {
124 gpio_direction_output(IOX_SHCP, 0);
125 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
126 udelay(500);
127 gpio_direction_output(IOX_SHCP, 1);
128 udelay(500);
129 }
130
131 gpio_direction_output(IOX_STCP, 0);
132 udelay(500);
133 /*
134 * shift register will be output to pins
135 */
136 gpio_direction_output(IOX_STCP, 1);
137
138 for (i = 7; i >= 0; i--) {
139 gpio_direction_output(IOX_SHCP, 0);
140 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
141 udelay(500);
142 gpio_direction_output(IOX_SHCP, 1);
143 udelay(500);
144 }
145 gpio_direction_output(IOX_STCP, 0);
146 udelay(500);
147 /*
148 * shift register will be output to pins
149 */
150 gpio_direction_output(IOX_STCP, 1);
151
152 gpio_direction_output(IOX_OE, 1);
153 };
154
155 void iox74lv_set(int index)
156 {
157 int i;
158
159 gpio_direction_output(IOX_OE, 0);
160
161 for (i = 7; i >= 0; i--) {
162 gpio_direction_output(IOX_SHCP, 0);
163
164 if (i == index)
165 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
166 else
167 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
168 udelay(500);
169 gpio_direction_output(IOX_SHCP, 1);
170 udelay(500);
171 }
172
173 gpio_direction_output(IOX_STCP, 0);
174 udelay(500);
175 /*
176 * shift register will be output to pins
177 */
178 gpio_direction_output(IOX_STCP, 1);
179
180 for (i = 7; i >= 0; i--) {
181 gpio_direction_output(IOX_SHCP, 0);
182 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
183 udelay(500);
184 gpio_direction_output(IOX_SHCP, 1);
185 udelay(500);
186 }
187
188 gpio_direction_output(IOX_STCP, 0);
189 udelay(500);
190 /*
191 * shift register will be output to pins
192 */
193 gpio_direction_output(IOX_STCP, 1);
194
195 gpio_direction_output(IOX_OE, 1);
196 };
197
198 #ifdef CONFIG_SYS_I2C_MXC
199 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
200 /* I2C1 for PMIC and EEPROM */
201 struct i2c_pads_info i2c_pad_info1 = {
202 .scl = {
203 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
204 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
205 .gp = IMX_GPIO_NR(1, 28),
206 },
207 .sda = {
208 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
209 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
210 .gp = IMX_GPIO_NR(1, 29),
211 },
212 };
213 #endif
214
215 int dram_init(void)
216 {
217 gd->ram_size = PHYS_SDRAM_SIZE;
218
219 return 0;
220 }
221
222 static iomux_v3_cfg_t const uart1_pads[] = {
223 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
224 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
225 };
226
227 static iomux_v3_cfg_t const usdhc1_pads[] = {
228 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
229 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
230 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
231 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
232 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
233 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
234
235 /* VSELECT */
236 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
237 /* CD */
238 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
239 /* RST_B */
240 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
241 };
242
243 /*
244 * mx6ul_14x14_evk board default supports sd card. If want to use
245 * EMMC, need to do board rework for sd2.
246 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
247 * emmc, need to define this macro.
248 */
249 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
250 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
251 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
252 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
253 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
254 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
255 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
256 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
257 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
258 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
259 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
260 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
261
262 /*
263 * RST_B
264 */
265 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
266 };
267 #else
268 static iomux_v3_cfg_t const usdhc2_pads[] = {
269 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
270 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
271 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
272 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
273 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
274 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
275 };
276
277 static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
278 /*
279 * The evk board uses DAT3 to detect CD card plugin,
280 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
281 */
282 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
283 };
284
285 static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
286 MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
287 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
288 };
289 #endif
290
291 static void setup_iomux_uart(void)
292 {
293 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
294 }
295
296 #ifdef CONFIG_FSL_QSPI
297
298 #define QSPI_PAD_CTRL1 \
299 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
300 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
301
302 static iomux_v3_cfg_t const quadspi_pads[] = {
303 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
304 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
305 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
306 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
307 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
308 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
309 };
310
311 int board_qspi_init(void)
312 {
313 /* Set the iomux */
314 imx_iomux_v3_setup_multiple_pads(quadspi_pads,
315 ARRAY_SIZE(quadspi_pads));
316 /* Set the clock */
317 enable_qspi_clk(0);
318
319 return 0;
320 }
321 #endif
322
323 #ifdef CONFIG_FSL_ESDHC
324 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
325 {USDHC1_BASE_ADDR, 0, 4},
326 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
327 {USDHC2_BASE_ADDR, 0, 8},
328 #else
329 {USDHC2_BASE_ADDR, 0, 4},
330 #endif
331 };
332
333 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
334 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
335 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
336 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
337
338 int board_mmc_getcd(struct mmc *mmc)
339 {
340 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
341 int ret = 0;
342
343 switch (cfg->esdhc_base) {
344 case USDHC1_BASE_ADDR:
345 ret = !gpio_get_value(USDHC1_CD_GPIO);
346 break;
347 case USDHC2_BASE_ADDR:
348 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
349 ret = 1;
350 #else
351 imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
352 ARRAY_SIZE(usdhc2_cd_pads));
353 gpio_direction_input(USDHC2_CD_GPIO);
354
355 /*
356 * Since it is the DAT3 pin, this pin is pulled to
357 * low voltage if no card
358 */
359 ret = gpio_get_value(USDHC2_CD_GPIO);
360
361 imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
362 ARRAY_SIZE(usdhc2_dat3_pads));
363 #endif
364 break;
365 }
366
367 return ret;
368 }
369
370 int board_mmc_init(bd_t *bis)
371 {
372 #ifdef CONFIG_SPL_BUILD
373 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
374 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
375 ARRAY_SIZE(usdhc2_emmc_pads));
376 #else
377 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
378 #endif
379 gpio_direction_output(USDHC2_PWR_GPIO, 0);
380 udelay(500);
381 gpio_direction_output(USDHC2_PWR_GPIO, 1);
382 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
383 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
384 #else
385 int i, ret;
386
387 /*
388 * According to the board_mmc_init() the following map is done:
389 * (U-boot device node) (Physical Port)
390 * mmc0 USDHC1
391 * mmc1 USDHC2
392 */
393 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
394 switch (i) {
395 case 0:
396 imx_iomux_v3_setup_multiple_pads(
397 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
398 gpio_direction_input(USDHC1_CD_GPIO);
399 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
400
401 gpio_direction_output(USDHC1_PWR_GPIO, 0);
402 udelay(500);
403 gpio_direction_output(USDHC1_PWR_GPIO, 1);
404 break;
405 case 1:
406 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
407 imx_iomux_v3_setup_multiple_pads(
408 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
409 #else
410 imx_iomux_v3_setup_multiple_pads(
411 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
412 #endif
413 gpio_direction_output(USDHC2_PWR_GPIO, 0);
414 udelay(500);
415 gpio_direction_output(USDHC2_PWR_GPIO, 1);
416 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
417 break;
418 default:
419 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
420 return -EINVAL;
421 }
422
423 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
424 if (ret) {
425 printf("Warning: failed to initialize mmc dev %d\n", i);
426 return ret;
427 }
428 }
429 #endif
430 return 0;
431 }
432 #endif
433
434 #ifdef CONFIG_USB_EHCI_MX6
435 #define USB_OTHERREGS_OFFSET 0x800
436 #define UCTRL_PWR_POL (1 << 9)
437
438 static iomux_v3_cfg_t const usb_otg_pads[] = {
439 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
440 };
441
442 /* At default the 3v3 enables the MIC2026 for VBUS power */
443 static void setup_usb(void)
444 {
445 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
446 ARRAY_SIZE(usb_otg_pads));
447 }
448
449 int board_usb_phy_mode(int port)
450 {
451 if (port == 1)
452 return USB_INIT_HOST;
453 else
454 return usb_phy_mode(port);
455 }
456
457 int board_ehci_hcd_init(int port)
458 {
459 u32 *usbnc_usb_ctrl;
460
461 if (port > 1)
462 return -EINVAL;
463
464 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
465 port * 4);
466
467 /* Set Power polarity */
468 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
469
470 return 0;
471 }
472 #endif
473
474 #ifdef CONFIG_FEC_MXC
475 /*
476 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
477 * be used for ENET1 or ENET2, cannot be used for both.
478 */
479 static iomux_v3_cfg_t const fec1_pads[] = {
480 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
481 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
482 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
483 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
484 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
485 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
486 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
487 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
488 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
489 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
490 };
491
492 static iomux_v3_cfg_t const fec2_pads[] = {
493 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
494 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
495
496 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
497 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
498 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
499 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
500
501 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
502 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
503 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
504 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
505 };
506
507 static void setup_iomux_fec(int fec_id)
508 {
509 if (fec_id == 0)
510 imx_iomux_v3_setup_multiple_pads(fec1_pads,
511 ARRAY_SIZE(fec1_pads));
512 else
513 imx_iomux_v3_setup_multiple_pads(fec2_pads,
514 ARRAY_SIZE(fec2_pads));
515 }
516
517 int board_eth_init(bd_t *bis)
518 {
519 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
520
521 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
522 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
523 }
524
525 static int setup_fec(int fec_id)
526 {
527 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
528 int ret;
529
530 if (fec_id == 0) {
531 /*
532 * Use 50M anatop loopback REF_CLK1 for ENET1,
533 * clear gpr1[13], set gpr1[17].
534 */
535 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
536 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
537 } else {
538 /*
539 * Use 50M anatop loopback REF_CLK2 for ENET2,
540 * clear gpr1[14], set gpr1[18].
541 */
542 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
543 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
544 }
545
546 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
547 if (ret)
548 return ret;
549
550 enable_enet_clk(1);
551
552 return 0;
553 }
554
555 int board_phy_config(struct phy_device *phydev)
556 {
557 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
558
559 if (phydev->drv->config)
560 phydev->drv->config(phydev);
561
562 return 0;
563 }
564 #endif
565
566 int board_early_init_f(void)
567 {
568 setup_iomux_uart();
569
570 return 0;
571 }
572
573 int board_init(void)
574 {
575 /* Address of boot parameters */
576 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
577
578 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
579
580 iox74lv_init();
581
582 #ifdef CONFIG_SYS_I2C_MXC
583 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
584 #endif
585
586 #ifdef CONFIG_FEC_MXC
587 setup_fec(CONFIG_FEC_ENET_DEV);
588 #endif
589
590 #ifdef CONFIG_USB_EHCI_MX6
591 setup_usb();
592 #endif
593
594 #ifdef CONFIG_FSL_QSPI
595 board_qspi_init();
596 #endif
597
598 return 0;
599 }
600
601 #ifdef CONFIG_CMD_BMODE
602 static const struct boot_mode board_boot_modes[] = {
603 /* 4 bit bus width */
604 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
605 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
606 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
607 {NULL, 0},
608 };
609 #endif
610
611 int board_late_init(void)
612 {
613 #ifdef CONFIG_CMD_BMODE
614 add_board_boot_modes(board_boot_modes);
615 #endif
616
617 return 0;
618 }
619
620 u32 get_board_rev(void)
621 {
622 return get_cpu_rev();
623 }
624
625 int checkboard(void)
626 {
627 puts("Board: MX6UL 14x14 EVK\n");
628
629 return 0;
630 }
631
632 #ifdef CONFIG_SPL_BUILD
633 #include <libfdt.h>
634 #include <spl.h>
635 #include <asm/arch/mx6-ddr.h>
636
637 const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
638 .dram_dqm0 = 0x00000030,
639 .dram_dqm1 = 0x00000030,
640 .dram_ras = 0x00000030,
641 .dram_cas = 0x00000030,
642 .dram_odt0 = 0x00000030,
643 .dram_odt1 = 0x00000030,
644 .dram_sdba2 = 0x00000000,
645 .dram_sdclk_0 = 0x00000008,
646 .dram_sdqs0 = 0x00000038,
647 .dram_sdqs1 = 0x00000030,
648 .dram_reset = 0x00000030,
649 };
650
651 const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
652 .grp_addds = 0x00000030,
653 .grp_ddrmode_ctl = 0x00020000,
654 .grp_b0ds = 0x00000030,
655 .grp_ctlds = 0x00000030,
656 .grp_b1ds = 0x00000030,
657 .grp_ddrpke = 0x00000000,
658 .grp_ddrmode = 0x00020000,
659 .grp_ddr_type = 0x000c0000,
660 };
661
662 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
663 .p0_mpwldectrl0 = 0x00070007,
664 .p0_mpdgctrl0 = 0x41490145,
665 .p0_mprddlctl = 0x40404546,
666 .p0_mpwrdlctl = 0x4040524D,
667 };
668
669 static struct mx6_ddr3_cfg mem_ddr = {
670 .mem_speed = 800,
671 .density = 4,
672 .width = 16,
673 .banks = 8,
674 .rowaddr = 15,
675 .coladdr = 10,
676 .pagesz = 2,
677 .trcd = 1375,
678 .trcmin = 4875,
679 .trasmin = 3500,
680 };
681
682 static void ccgr_init(void)
683 {
684 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
685
686 writel(0xFFFFFFFF, &ccm->CCGR0);
687 writel(0xFFFFFFFF, &ccm->CCGR1);
688 writel(0xFFFFFFFF, &ccm->CCGR2);
689 writel(0xFFFFFFFF, &ccm->CCGR3);
690 writel(0xFFFFFFFF, &ccm->CCGR4);
691 writel(0xFFFFFFFF, &ccm->CCGR5);
692 writel(0xFFFFFFFF, &ccm->CCGR6);
693 writel(0xFFFFFFFF, &ccm->CCGR7);
694 }
695
696 static void spl_dram_init(void)
697 {
698 struct mx6_ddr_sysinfo sysinfo = {
699 .dsize = 0,
700 .cs_density = 20,
701 .ncs = 1,
702 .cs1_mirror = 0,
703 .rtt_wr = 2,
704 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
705 .walat = 1, /* Write additional latency */
706 .ralat = 5, /* Read additional latency */
707 .mif3_mode = 3, /* Command prediction working mode */
708 .bi_on = 1, /* Bank interleaving enabled */
709 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
710 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
711 .ddr_type = DDR_TYPE_DDR3,
712 };
713
714 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
715 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
716 }
717
718 void board_init_f(ulong dummy)
719 {
720 /* setup AIPS and disable watchdog */
721 arch_cpu_init();
722
723 ccgr_init();
724
725 /* iomux and setup of i2c */
726 board_early_init_f();
727
728 /* setup GP timer */
729 timer_init();
730
731 /* UART clocks enabled and gd valid - init serial console */
732 preloader_console_init();
733
734 /* DDR initialization */
735 spl_dram_init();
736
737 /* Clear the BSS. */
738 memset(__bss_start, 0, __bss_end - __bss_start);
739
740 /* load/boot image from boot device */
741 board_init_r(NULL, 0);
742 }
743
744 void reset_cpu(ulong addr)
745 {
746 }
747 #endif
"Das U-Boot" Source Tree