2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clock.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/mx7-pins.h>
10 #include <asm/arch/sys_proto.h>
12 #include <asm/mach-imx/iomux-v3.h>
14 #include <linux/sizes.h>
16 #include <fsl_esdhc.h>
20 #include <power/pmic.h>
21 #include <power/pfuze3000_pmic.h>
22 #include "../common/pfuze.h"
24 #include <asm/mach-imx/mxc_i2c.h>
25 #include <asm/arch/crm_regs.h>
27 DECLARE_GLOBAL_DATA_PTR
;
29 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
30 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
32 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
33 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
35 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
37 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
38 PAD_CTL_DSE_3P3V_49OHM)
40 #define QSPI_PAD_CTRL \
41 (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
43 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
45 #define SPI_PAD_CTRL \
46 (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
48 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
51 static iomux_v3_cfg_t
const ecspi3_pads
[] = {
52 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
53 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
54 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
55 MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22
| MUX_PAD_CTRL(NO_PAD_CTRL
),
58 int board_spi_cs_gpio(unsigned bus
, unsigned cs
)
60 return (bus
== 2 && cs
== 0) ? (IMX_GPIO_NR(6, 22)) : -1;
63 static void setup_spi(void)
65 imx_iomux_v3_setup_multiple_pads(ecspi3_pads
, ARRAY_SIZE(ecspi3_pads
));
71 gd
->ram_size
= PHYS_SDRAM_SIZE
;
76 static iomux_v3_cfg_t
const wdog_pads
[] = {
77 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B
| MUX_PAD_CTRL(NO_PAD_CTRL
),
80 static iomux_v3_cfg_t
const uart1_pads
[] = {
81 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
82 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
85 #ifdef CONFIG_NAND_MXS
86 static iomux_v3_cfg_t
const gpmi_pads
[] = {
87 MX7D_PAD_SD3_DATA0__NAND_DATA00
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
88 MX7D_PAD_SD3_DATA1__NAND_DATA01
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
89 MX7D_PAD_SD3_DATA2__NAND_DATA02
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
90 MX7D_PAD_SD3_DATA3__NAND_DATA03
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
91 MX7D_PAD_SD3_DATA4__NAND_DATA04
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
92 MX7D_PAD_SD3_DATA5__NAND_DATA05
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
93 MX7D_PAD_SD3_DATA6__NAND_DATA06
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
94 MX7D_PAD_SD3_DATA7__NAND_DATA07
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
95 MX7D_PAD_SD3_CLK__NAND_CLE
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
96 MX7D_PAD_SD3_CMD__NAND_ALE
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
97 MX7D_PAD_SD3_STROBE__NAND_RE_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
98 MX7D_PAD_SD3_RESET_B__NAND_WE_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
99 MX7D_PAD_SAI1_MCLK__NAND_WP_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
100 MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
101 MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
102 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
103 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
104 MX7D_PAD_SAI1_TX_SYNC__NAND_DQS
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
105 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B
| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL
),
108 static void setup_gpmi_nand(void)
110 imx_iomux_v3_setup_multiple_pads(gpmi_pads
, ARRAY_SIZE(gpmi_pads
));
112 /* NAND_USDHC_BUS_CLK is set in rom */
117 #ifdef CONFIG_VIDEO_MXS
118 static iomux_v3_cfg_t
const lcd_pads
[] = {
119 MX7D_PAD_LCD_CLK__LCD_CLK
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
120 MX7D_PAD_LCD_ENABLE__LCD_ENABLE
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
121 MX7D_PAD_LCD_HSYNC__LCD_HSYNC
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
122 MX7D_PAD_LCD_VSYNC__LCD_VSYNC
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
123 MX7D_PAD_LCD_DATA00__LCD_DATA0
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
124 MX7D_PAD_LCD_DATA01__LCD_DATA1
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
125 MX7D_PAD_LCD_DATA02__LCD_DATA2
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
126 MX7D_PAD_LCD_DATA03__LCD_DATA3
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
127 MX7D_PAD_LCD_DATA04__LCD_DATA4
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
128 MX7D_PAD_LCD_DATA05__LCD_DATA5
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
129 MX7D_PAD_LCD_DATA06__LCD_DATA6
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
130 MX7D_PAD_LCD_DATA07__LCD_DATA7
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
131 MX7D_PAD_LCD_DATA08__LCD_DATA8
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
132 MX7D_PAD_LCD_DATA09__LCD_DATA9
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
133 MX7D_PAD_LCD_DATA10__LCD_DATA10
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
134 MX7D_PAD_LCD_DATA11__LCD_DATA11
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
135 MX7D_PAD_LCD_DATA12__LCD_DATA12
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
136 MX7D_PAD_LCD_DATA13__LCD_DATA13
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
137 MX7D_PAD_LCD_DATA14__LCD_DATA14
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
138 MX7D_PAD_LCD_DATA15__LCD_DATA15
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
139 MX7D_PAD_LCD_DATA16__LCD_DATA16
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
140 MX7D_PAD_LCD_DATA17__LCD_DATA17
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
141 MX7D_PAD_LCD_DATA18__LCD_DATA18
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
142 MX7D_PAD_LCD_DATA19__LCD_DATA19
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
143 MX7D_PAD_LCD_DATA20__LCD_DATA20
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
144 MX7D_PAD_LCD_DATA21__LCD_DATA21
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
145 MX7D_PAD_LCD_DATA22__LCD_DATA22
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
146 MX7D_PAD_LCD_DATA23__LCD_DATA23
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
148 MX7D_PAD_LCD_RESET__GPIO3_IO4
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
151 static iomux_v3_cfg_t
const pwm_pads
[] = {
152 /* Use GPIO for Brightness adjustment, duty cycle = period */
153 MX7D_PAD_GPIO1_IO01__GPIO1_IO1
| MUX_PAD_CTRL(NO_PAD_CTRL
),
156 static int setup_lcd(void)
158 imx_iomux_v3_setup_multiple_pads(lcd_pads
, ARRAY_SIZE(lcd_pads
));
160 imx_iomux_v3_setup_multiple_pads(pwm_pads
, ARRAY_SIZE(pwm_pads
));
163 gpio_request(IMX_GPIO_NR(3, 4), "lcd reset");
164 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
166 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
168 /* Set Brightness to high */
169 gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight");
170 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
176 #ifdef CONFIG_FEC_MXC
177 static iomux_v3_cfg_t
const fec1_pads
[] = {
178 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
179 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
180 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
181 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
182 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
183 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
184 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
185 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
186 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
187 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
188 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
189 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
190 MX7D_PAD_GPIO1_IO10__ENET1_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL_MII
),
191 MX7D_PAD_GPIO1_IO11__ENET1_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL_MII
),
194 static void setup_iomux_fec(void)
196 imx_iomux_v3_setup_multiple_pads(fec1_pads
, ARRAY_SIZE(fec1_pads
));
200 static void setup_iomux_uart(void)
202 imx_iomux_v3_setup_multiple_pads(uart1_pads
, ARRAY_SIZE(uart1_pads
));
205 int board_mmc_get_env_dev(int devno
)
213 int mmc_map_to_kernel_blk(int dev_no
)
221 #ifdef CONFIG_FEC_MXC
222 int board_eth_init(bd_t
*bis
)
227 ret
= gpio_lookup_name("gpio_spi@0_5", NULL
, NULL
, &gpio
);
229 printf("GPIO: 'gpio_spi@0_5' not found\n");
233 ret
= gpio_request(gpio
, "fec_rst");
234 if (ret
&& ret
!= -EBUSY
) {
235 printf("gpio: requesting pin %u failed\n", gpio
);
239 gpio_direction_output(gpio
, 0);
241 gpio_direction_output(gpio
, 1);
245 ret
= fecmxc_initialize_multi(bis
, 0,
246 CONFIG_FEC_MXC_PHYADDR
, IMX_FEC_BASE
);
248 printf("FEC1 MXC: %s:failed\n", __func__
);
253 static int setup_fec(void)
255 struct iomuxc_gpr_base_regs
*const iomuxc_gpr_regs
256 = (struct iomuxc_gpr_base_regs
*) IOMUXC_GPR_BASE_ADDR
;
258 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
259 clrsetbits_le32(&iomuxc_gpr_regs
->gpr
[1],
260 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK
|
261 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK
), 0);
263 return set_clk_enet(ENET_125MHz
);
267 int board_phy_config(struct phy_device
*phydev
)
269 /* enable rgmii rxc skew and phy mode select to RGMII copper */
270 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x21);
271 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1f, 0x7ea8);
272 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x2f);
273 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1f, 0x71b7);
275 if (phydev
->drv
->config
)
276 phydev
->drv
->config(phydev
);
281 #ifdef CONFIG_FSL_QSPI
282 static iomux_v3_cfg_t
const quadspi_pads
[] = {
283 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
284 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
285 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
286 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
287 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
288 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
291 int board_qspi_init(void)
294 imx_iomux_v3_setup_multiple_pads(quadspi_pads
,
295 ARRAY_SIZE(quadspi_pads
));
304 int board_early_init_f(void)
313 /* address of boot parameters */
314 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
316 #ifdef CONFIG_FEC_MXC
320 #ifdef CONFIG_NAND_MXS
324 #ifdef CONFIG_VIDEO_MXS
328 #ifdef CONFIG_FSL_QSPI
332 #ifdef CONFIG_MXC_SPI
339 #ifdef CONFIG_DM_PMIC
340 int power_init_board(void)
343 int ret
, dev_id
, rev_id
;
345 ret
= pmic_get("pfuze3000", &dev
);
351 dev_id
= pmic_reg_read(dev
, PFUZE3000_DEVICEID
);
352 rev_id
= pmic_reg_read(dev
, PFUZE3000_REVID
);
353 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id
, rev_id
);
355 pmic_clrsetbits(dev
, PFUZE3000_LDOGCTL
, 0, 1);
358 * Set the voltage of VLDO4 output to 2.8V which feeds
359 * the MIPI DSI and MIPI CSI inputs.
361 pmic_clrsetbits(dev
, PFUZE3000_VLD4CTL
, 0xF, 0xA);
367 int board_late_init(void)
369 struct wdog_regs
*wdog
= (struct wdog_regs
*)WDOG1_BASE_ADDR
;
371 imx_iomux_v3_setup_multiple_pads(wdog_pads
, ARRAY_SIZE(wdog_pads
));
373 set_wdog_reset(wdog
);
376 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
377 * since we use PMIC_PWRON to reset the board.
379 clrsetbits_le16(&wdog
->wcr
, 0, 0x10);
388 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT
))
393 printf("Board: i.MX7D SABRESD in %s mode\n", mode
);