board/freescale/p1010rdb/p1010rdb.c

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/processor.h>
   9 #include <asm/mmu.h>
  10 #include <asm/cache.h>
  11 #include <asm/immap_85xx.h>
  12 #include <asm/io.h>
  13 #include <miiphy.h>
  14 #include <libfdt.h>
  15 #include <fdt_support.h>
  16 #include <fsl_mdio.h>
  17 #include <tsec.h>
  18 #include <mmc.h>
  19 #include <netdev.h>
  20 #include <pci.h>
  21 #include <asm/fsl_serdes.h>
  22 #include <asm/fsl_ifc.h>
  23 #include <asm/fsl_pci.h>
  24
  25 #ifndef CONFIG_SDCARD
  26 #include <hwconfig.h>
  27 #endif
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define GPIO4_PCIE_RESET_SET            0x08000000
  32 #define MUX_CPLD_CAN_UART               0x00
  33 #define MUX_CPLD_TDM                    0x01
  34 #define MUX_CPLD_SPICS0_FLASH           0x00
  35 #define MUX_CPLD_SPICS0_SLIC            0x02
  36
  37 #ifndef CONFIG_SDCARD
  38 struct cpld_data {
  39         u8 cpld_ver; /* cpld revision */
  40         u8 pcba_ver; /* pcb revision number */
  41         u8 twindie_ddr3;
  42         u8 res1[6];
  43         u8 bank_sel; /* NOR Flash bank */
  44         u8 res2[5];
  45         u8 usb2_sel;
  46         u8 res3[1];
  47         u8 porsw_sel;
  48         u8 tdm_can_sel;
  49         u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
  50         u8 por0; /* POR Options */
  51         u8 por1; /* POR Options */
  52         u8 por2; /* POR Options */
  53         u8 por3; /* POR Options */
  54 };
  55
  56 void cpld_show(void)
  57 {
  58         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  59
  60         printf("CPLD: V%x.%x PCBA: V%x.0\n",
  61                 in_8(&cpld_data->cpld_ver) & 0xF0,
  62                 in_8(&cpld_data->cpld_ver) & 0x0F,
  63                 in_8(&cpld_data->pcba_ver) & 0x0F);
  64
  65 #ifdef CONFIG_DEBUG
  66         printf("twindie_ddr =%x\n",
  67                 in_8(&cpld_data->twindie_ddr3));
  68         printf("bank_sel =%x\n",
  69                 in_8(&cpld_data->bank_sel));
  70         printf("usb2_sel =%x\n",
  71                 in_8(&cpld_data->usb2_sel));
  72         printf("porsw_sel =%x\n",
  73                 in_8(&cpld_data->porsw_sel));
  74         printf("tdm_can_sel =%x\n",
  75                 in_8(&cpld_data->tdm_can_sel));
  76         printf("tdm_can_sel =%x\n",
  77                 in_8(&cpld_data->tdm_can_sel));
  78         printf("spi_cs0_sel =%x\n",
  79                 in_8(&cpld_data->spi_cs0_sel));
  80         printf("bcsr0 =%x\n",
  81                 in_8(&cpld_data->bcsr0));
  82         printf("bcsr1 =%x\n",
  83                 in_8(&cpld_data->bcsr1));
  84         printf("bcsr2 =%x\n",
  85                 in_8(&cpld_data->bcsr2));
  86         printf("bcsr3 =%x\n",
  87                 in_8(&cpld_data->bcsr3));
  88 #endif
  89 }
  90 #endif
  91
  92 int board_early_init_f(void)
  93 {
  94         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  95 #ifndef CONFIG_SDCARD
  96         struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
  97
  98         /* Clock configuration to access CPLD using IFC(GPCM) */
  99         setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
 100 #endif
 101         /*
 102         * Reset PCIe slots via GPIO4
 103         */
 104         setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
 105         setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
 106
 107         return 0;
 108 }
 109
 110 int board_early_init_r(void)
 111 {
 112 #ifndef CONFIG_SDCARD
 113         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 114         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 115
 116         /*
 117          * Remap Boot flash region to caching-inhibited
 118          * so that flash can be erased properly.
 119          */
 120
 121         /* Flush d-cache and invalidate i-cache of any FLASH data */
 122         flush_dcache();
 123         invalidate_icache();
 124
 125         /* invalidate existing TLB entry for flash */
 126         disable_tlb(flash_esel);
 127
 128         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 129                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 130                         0, flash_esel, BOOKE_PAGESZ_16M, 1);
 131
 132         set_tlb(1, flashbase + 0x1000000,
 133                         CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 134                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 135                         0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
 136 #endif
 137         return 0;
 138 }
 139
 140 #ifdef CONFIG_PCI
 141 void pci_init_board(void)
 142 {
 143         fsl_pcie_init_board(0);
 144 }
 145 #endif /* ifdef CONFIG_PCI */
 146
 147 int checkboard(void)
 148 {
 149         struct cpu_type *cpu;
 150
 151         cpu = gd->arch.cpu;
 152         printf("Board: %sRDB\n", cpu->name);
 153
 154         return 0;
 155 }
 156
 157 #ifdef CONFIG_TSEC_ENET
 158 int board_eth_init(bd_t *bis)
 159 {
 160         struct fsl_pq_mdio_info mdio_info;
 161         struct tsec_info_struct tsec_info[4];
 162         struct cpu_type *cpu;
 163         int num = 0;
 164
 165         cpu = gd->arch.cpu;
 166
 167 #ifdef CONFIG_TSEC1
 168         SET_STD_TSEC_INFO(tsec_info[num], 1);
 169         num++;
 170 #endif
 171 #ifdef CONFIG_TSEC2
 172         SET_STD_TSEC_INFO(tsec_info[num], 2);
 173         num++;
 174 #endif
 175 #ifdef CONFIG_TSEC3
 176         /* P1014 and it's derivatives do not support eTSEC3 */
 177         if (cpu->soc_ver != SVR_P1014) {
 178                 SET_STD_TSEC_INFO(tsec_info[num], 3);
 179                 num++;
 180         }
 181 #endif
 182         if (!num) {
 183                 printf("No TSECs initialized\n");
 184                 return 0;
 185         }
 186
 187         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 188         mdio_info.name = DEFAULT_MII_NAME;
 189
 190         fsl_pq_mdio_init(bis, &mdio_info);
 191
 192         tsec_eth_init(bis, tsec_info, num);
 193
 194         return pci_eth_init(bis);
 195 }
 196 #endif
 197
 198 #if defined(CONFIG_OF_BOARD_SETUP)
 199 void fdt_del_flexcan(void *blob)
 200 {
 201         int nodeoff = 0;
 202
 203         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 204                                 "fsl,p1010-flexcan")) >= 0) {
 205                 fdt_del_node(blob, nodeoff);
 206         }
 207 }
 208
 209 void fdt_del_spi_flash(void *blob)
 210 {
 211         int nodeoff = 0;
 212
 213         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 214                                 "spansion,s25sl12801")) >= 0) {
 215                 fdt_del_node(blob, nodeoff);
 216         }
 217 }
 218
 219 void fdt_del_spi_slic(void *blob)
 220 {
 221         int nodeoff = 0;
 222
 223         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 224                                 "zarlink,le88266")) >= 0) {
 225                 fdt_del_node(blob, nodeoff);
 226         }
 227 }
 228
 229 void fdt_del_tdm(void *blob)
 230 {
 231         int nodeoff = 0;
 232
 233         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 234                                 "fsl,starlite-tdm")) >= 0) {
 235                 fdt_del_node(blob, nodeoff);
 236         }
 237 }
 238
 239 void fdt_del_sdhc(void *blob)
 240 {
 241         int nodeoff = 0;
 242
 243         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 244                         "fsl,esdhc")) >= 0) {
 245                 fdt_del_node(blob, nodeoff);
 246         }
 247 }
 248
 249 void fdt_disable_uart1(void *blob)
 250 {
 251         int nodeoff;
 252
 253         nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
 254                                         CONFIG_SYS_NS16550_COM2);
 255
 256         if (nodeoff > 0) {
 257                 fdt_status_disabled(blob, nodeoff);
 258         } else {
 259                 printf("WARNING unable to set status for fsl,ns16550 "
 260                         "uart1: %s\n", fdt_strerror(nodeoff));
 261         }
 262 }
 263
 264 void ft_board_setup(void *blob, bd_t *bd)
 265 {
 266         phys_addr_t base;
 267         phys_size_t size;
 268         struct cpu_type *cpu;
 269
 270         cpu = gd->arch.cpu;
 271
 272         ft_cpu_setup(blob, bd);
 273
 274         base = getenv_bootm_low();
 275         size = getenv_bootm_size();
 276
 277 #if defined(CONFIG_PCI)
 278         FT_FSL_PCI_SETUP;
 279 #endif
 280
 281         fdt_fixup_memory(blob, (u64)base, (u64)size);
 282
 283 #if defined(CONFIG_HAS_FSL_DR_USB)
 284         fdt_fixup_dr_usb(blob, bd);
 285 #endif
 286
 287        /* P1014 and it's derivatives don't support CAN and eTSEC3 */
 288         if (cpu->soc_ver == SVR_P1014) {
 289                 fdt_del_flexcan(blob);
 290                 fdt_del_node_and_alias(blob, "ethernet2");
 291         }
 292 #ifndef CONFIG_SDCARD
 293         /* disable sdhc due to sdhc bug */
 294         fdt_del_sdhc(blob);
 295         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 296                 fdt_del_tdm(blob);
 297                 fdt_del_spi_slic(blob);
 298         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 299                 fdt_del_flexcan(blob);
 300                 fdt_del_spi_flash(blob);
 301                 fdt_disable_uart1(blob);
 302         } else {
 303                 /*
 304                  * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
 305                  * explicitly, defaultly spi_cs_sel to spi-flash instead of
 306                  * to tdm/slic.
 307                  */
 308                 fdt_del_tdm(blob);
 309                 fdt_del_flexcan(blob);
 310                 fdt_disable_uart1(blob);
 311         }
 312 #endif
 313 }
 314 #endif
 315
 316 #ifndef CONFIG_SDCARD
 317 int misc_init_r(void)
 318 {
 319         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 320         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 321
 322         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 323                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
 324                                 MPC85xx_PMUXCR_CAN1_UART |
 325                                 MPC85xx_PMUXCR_CAN2_TDM |
 326                                 MPC85xx_PMUXCR_CAN2_UART);
 327                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
 328         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 329                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
 330                                 MPC85xx_PMUXCR_CAN1_UART);
 331                 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
 332                                 MPC85xx_PMUXCR_CAN1_TDM);
 333                 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
 334                 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
 335                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
 336                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
 337         } else {
 338                 /* defaultly spi_cs_sel to flash */
 339                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
 340         }
 341
 342         return 0;
 343 }
 344 #endif