board/freescale/p1022ds/spl_minimal.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <ns16550.h>
   9 #include <asm/io.h>
  10 #include <nand.h>
  11 #include <asm/fsl_law.h>
  12 #include <asm/fsl_ddr_sdram.h>
  13
  14
  15 /*
  16  * Fixed sdram init -- doesn't use serial presence detect.
  17  */
  18 void sdram_init(void)
  19 {
  20         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
  21
  22         __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
  23         __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
  24 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
  25         __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
  26         __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
  27 #endif
  28         __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
  29         __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
  30         __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
  31         __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
  32
  33         __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
  34         __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
  35         __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
  36
  37         __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
  38         __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
  39         __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
  40
  41         __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
  42         __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
  43         __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
  44         __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
  45
  46         /* Set, but do not enable the memory */
  47         __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN,
  48                         &ddr->sdram_cfg);
  49
  50         in_be32(&ddr->sdram_cfg);
  51         udelay(500);
  52
  53         /* Let the controller go */
  54         out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
  55         in_be32(&ddr->sdram_cfg);
  56
  57         set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
  58 }
  59
  60 const static u32 sysclk_tbl[] = {
  61         66666000, 7499900, 83332500, 8999900,
  62         99999000, 11111000, 12499800, 13333200
  63 };
  64
  65 void board_init_f(ulong bootflag)
  66 {
  67         int px_spd;
  68         u32 plat_ratio, sys_clk, bus_clk;
  69         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  70
  71         /* for FPGA */
  72         set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
  73         set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  74
  75         /* initialize selected port with appropriate baud rate */
  76         px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
  77         sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
  78         plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  79         bus_clk = sys_clk * plat_ratio / 2;
  80
  81         NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  82                         bus_clk / 16 / CONFIG_BAUDRATE);
  83
  84         puts("\nNAND boot... ");
  85
  86         /* Initialize the DDR3 */
  87         sdram_init();
  88
  89         /* copy code to RAM and jump to it - this should not return */
  90         /* NOTE - code has to be copied out of NAND buffer before
  91          * other blocks can be read.
  92          */
  93         relocate_code(CONFIG_SPL_RELOC_STACK, 0,
  94                         CONFIG_SPL_RELOC_TEXT_BASE);
  95 }
  96
  97 void board_init_r(gd_t *gd, ulong dest_addr)
  98 {
  99         nand_boot();
 100 }
 101
 102 void putc(char c)
 103 {
 104         if (c == '\n')
 105                 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
 106
 107         NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
 108 }
 109
 110 void puts(const char *str)
 111 {
 112         while (*str)
 113                 putc(*str++);
 114 }