2 * Copyright 2009, 2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/immap_85xx.h>
10 #include <asm/processor.h>
11 #include <asm/fsl_ddr_sdram.h>
13 #include <asm/fsl_law.h>
15 DECLARE_GLOBAL_DATA_PTR
;
17 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
18 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
19 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
20 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
21 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
22 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
23 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
24 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
25 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
26 #define CONFIG_SYS_DDR_RCW_1 0x00000000
27 #define CONFIG_SYS_DDR_RCW_2 0x00000000
28 #define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/
29 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
30 #define CONFIG_SYS_DDR_TIMING_4 0x00000000
31 #define CONFIG_SYS_DDR_TIMING_5 0x00000000
33 #define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
34 #define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
35 #define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
36 #define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
37 #define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
38 #define CONFIG_SYS_DDR_MODE_1_400 0x00480432
39 #define CONFIG_SYS_DDR_MODE_2_400 0x00000000
40 #define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
42 #define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
43 #define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
44 #define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
45 #define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
46 #define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
47 #define CONFIG_SYS_DDR_MODE_1_533 0x00040642
48 #define CONFIG_SYS_DDR_MODE_2_533 0x00000000
49 #define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
51 #define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
52 #define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
53 #define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
54 #define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
55 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
56 #define CONFIG_SYS_DDR_MODE_1_667 0x00040852
57 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
58 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
60 #define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
61 #define CONFIG_SYS_DDR_TIMING_0_800 0x00770802
62 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
63 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
64 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
65 #define CONFIG_SYS_DDR_MODE_1_800 0x00040852
66 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
67 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
69 fsl_ddr_cfg_regs_t ddr_cfg_regs_400
= {
70 .cs
[0].bnds
= CONFIG_SYS_DDR_CS0_BNDS
,
71 .cs
[0].config
= CONFIG_SYS_DDR_CS0_CONFIG
,
72 .cs
[0].config_2
= CONFIG_SYS_DDR_CS0_CONFIG_2
,
73 .timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3_400
,
74 .timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0_400
,
75 .timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1_400
,
76 .timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2_400
,
77 .ddr_sdram_cfg
= CONFIG_SYS_DDR_CONTROL
,
78 .ddr_sdram_cfg_2
= CONFIG_SYS_DDR_CONTROL_2
,
79 .ddr_sdram_mode
= CONFIG_SYS_DDR_MODE_1_400
,
80 .ddr_sdram_mode_2
= CONFIG_SYS_DDR_MODE_2_400
,
81 .ddr_sdram_md_cntl
= CONFIG_SYS_DDR_MODE_CONTROL
,
82 .ddr_sdram_interval
= CONFIG_SYS_DDR_INTERVAL_400
,
83 .ddr_data_init
= CONFIG_MEM_INIT_VALUE
,
84 .ddr_sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL_400
,
85 .ddr_init_addr
= CONFIG_SYS_DDR_INIT_ADDR
,
86 .ddr_init_ext_addr
= CONFIG_SYS_DDR_INIT_EXT_ADDR
,
87 .timing_cfg_4
= CONFIG_SYS_DDR_TIMING_4
,
88 .timing_cfg_5
= CONFIG_SYS_DDR_TIMING_5
,
89 .ddr_zq_cntl
= CONFIG_SYS_DDR_ZQ_CONTROL
,
90 .ddr_wrlvl_cntl
= CONFIG_SYS_DDR_WRLVL_CONTROL
,
91 .ddr_sr_cntr
= CONFIG_SYS_DDR_SR_CNTR
,
92 .ddr_sdram_rcw_1
= CONFIG_SYS_DDR_RCW_1
,
93 .ddr_sdram_rcw_2
= CONFIG_SYS_DDR_RCW_2
96 fsl_ddr_cfg_regs_t ddr_cfg_regs_533
= {
97 .cs
[0].bnds
= CONFIG_SYS_DDR_CS0_BNDS
,
98 .cs
[0].config
= CONFIG_SYS_DDR_CS0_CONFIG
,
99 .cs
[0].config_2
= CONFIG_SYS_DDR_CS0_CONFIG_2
,
100 .timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3_533
,
101 .timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0_533
,
102 .timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1_533
,
103 .timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2_533
,
104 .ddr_sdram_cfg
= CONFIG_SYS_DDR_CONTROL
,
105 .ddr_sdram_cfg_2
= CONFIG_SYS_DDR_CONTROL_2
,
106 .ddr_sdram_mode
= CONFIG_SYS_DDR_MODE_1_533
,
107 .ddr_sdram_mode_2
= CONFIG_SYS_DDR_MODE_2_533
,
108 .ddr_sdram_md_cntl
= CONFIG_SYS_DDR_MODE_CONTROL
,
109 .ddr_sdram_interval
= CONFIG_SYS_DDR_INTERVAL_533
,
110 .ddr_data_init
= CONFIG_MEM_INIT_VALUE
,
111 .ddr_sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL_533
,
112 .ddr_init_addr
= CONFIG_SYS_DDR_INIT_ADDR
,
113 .ddr_init_ext_addr
= CONFIG_SYS_DDR_INIT_EXT_ADDR
,
114 .timing_cfg_4
= CONFIG_SYS_DDR_TIMING_4
,
115 .timing_cfg_5
= CONFIG_SYS_DDR_TIMING_5
,
116 .ddr_zq_cntl
= CONFIG_SYS_DDR_ZQ_CONTROL
,
117 .ddr_wrlvl_cntl
= CONFIG_SYS_DDR_WRLVL_CONTROL
,
118 .ddr_sr_cntr
= CONFIG_SYS_DDR_SR_CNTR
,
119 .ddr_sdram_rcw_1
= CONFIG_SYS_DDR_RCW_1
,
120 .ddr_sdram_rcw_2
= CONFIG_SYS_DDR_RCW_2
123 fsl_ddr_cfg_regs_t ddr_cfg_regs_667
= {
124 .cs
[0].bnds
= CONFIG_SYS_DDR_CS0_BNDS
,
125 .cs
[0].config
= CONFIG_SYS_DDR_CS0_CONFIG
,
126 .cs
[0].config_2
= CONFIG_SYS_DDR_CS0_CONFIG_2
,
127 .timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3_667
,
128 .timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0_667
,
129 .timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1_667
,
130 .timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2_667
,
131 .ddr_sdram_cfg
= CONFIG_SYS_DDR_CONTROL
,
132 .ddr_sdram_cfg_2
= CONFIG_SYS_DDR_CONTROL_2
,
133 .ddr_sdram_mode
= CONFIG_SYS_DDR_MODE_1_667
,
134 .ddr_sdram_mode_2
= CONFIG_SYS_DDR_MODE_2_667
,
135 .ddr_sdram_md_cntl
= CONFIG_SYS_DDR_MODE_CONTROL
,
136 .ddr_sdram_interval
= CONFIG_SYS_DDR_INTERVAL_667
,
137 .ddr_data_init
= CONFIG_MEM_INIT_VALUE
,
138 .ddr_sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL_667
,
139 .ddr_init_addr
= CONFIG_SYS_DDR_INIT_ADDR
,
140 .ddr_init_ext_addr
= CONFIG_SYS_DDR_INIT_EXT_ADDR
,
141 .timing_cfg_4
= CONFIG_SYS_DDR_TIMING_4
,
142 .timing_cfg_5
= CONFIG_SYS_DDR_TIMING_5
,
143 .ddr_zq_cntl
= CONFIG_SYS_DDR_ZQ_CONTROL
,
144 .ddr_wrlvl_cntl
= CONFIG_SYS_DDR_WRLVL_CONTROL
,
145 .ddr_sr_cntr
= CONFIG_SYS_DDR_SR_CNTR
,
146 .ddr_sdram_rcw_1
= CONFIG_SYS_DDR_RCW_1
,
147 .ddr_sdram_rcw_2
= CONFIG_SYS_DDR_RCW_2
150 fsl_ddr_cfg_regs_t ddr_cfg_regs_800
= {
151 .cs
[0].bnds
= CONFIG_SYS_DDR_CS0_BNDS
,
152 .cs
[0].config
= CONFIG_SYS_DDR_CS0_CONFIG
,
153 .cs
[0].config_2
= CONFIG_SYS_DDR_CS0_CONFIG_2
,
154 .timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3_800
,
155 .timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0_800
,
156 .timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1_800
,
157 .timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2_800
,
158 .ddr_sdram_cfg
= CONFIG_SYS_DDR_CONTROL
,
159 .ddr_sdram_cfg_2
= CONFIG_SYS_DDR_CONTROL_2
,
160 .ddr_sdram_mode
= CONFIG_SYS_DDR_MODE_1_800
,
161 .ddr_sdram_mode_2
= CONFIG_SYS_DDR_MODE_2_800
,
162 .ddr_sdram_md_cntl
= CONFIG_SYS_DDR_MODE_CONTROL
,
163 .ddr_sdram_interval
= CONFIG_SYS_DDR_INTERVAL_800
,
164 .ddr_data_init
= CONFIG_MEM_INIT_VALUE
,
165 .ddr_sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL_800
,
166 .ddr_init_addr
= CONFIG_SYS_DDR_INIT_ADDR
,
167 .ddr_init_ext_addr
= CONFIG_SYS_DDR_INIT_EXT_ADDR
,
168 .timing_cfg_4
= CONFIG_SYS_DDR_TIMING_4
,
169 .timing_cfg_5
= CONFIG_SYS_DDR_TIMING_5
,
170 .ddr_zq_cntl
= CONFIG_SYS_DDR_ZQ_CONTROL
,
171 .ddr_wrlvl_cntl
= CONFIG_SYS_DDR_WRLVL_CONTROL
,
172 .ddr_sr_cntr
= CONFIG_SYS_DDR_SR_CNTR
,
173 .ddr_sdram_rcw_1
= CONFIG_SYS_DDR_RCW_1
,
174 .ddr_sdram_rcw_2
= CONFIG_SYS_DDR_RCW_2
178 * Fixed sdram init -- doesn't use serial presence detect.
181 phys_size_t
fixed_sdram (void)
184 fsl_ddr_cfg_regs_t ddr_cfg_regs
;
186 struct cpu_type
*cpu
;
187 ulong ddr_freq
, ddr_freq_mhz
;
190 /* P1020 and it's derivatives support max 32bit DDR width */
191 if (cpu
->soc_ver
== SVR_P1020
|| cpu
->soc_ver
== SVR_P1011
) {
192 ddr_size
= (CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024 / 2);
194 ddr_size
= CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;
196 #if defined(CONFIG_SYS_RAMBOOT)
199 ddr_freq
= get_ddr_freq(0);
200 ddr_freq_mhz
= ddr_freq
/ 1000000;
202 printf("Configuring DDR for %s MT/s data rate\n",
203 strmhz(buf
, ddr_freq
));
205 if(ddr_freq_mhz
<= 400)
206 memcpy(&ddr_cfg_regs
, &ddr_cfg_regs_400
, sizeof(ddr_cfg_regs
));
207 else if(ddr_freq_mhz
<= 533)
208 memcpy(&ddr_cfg_regs
, &ddr_cfg_regs_533
, sizeof(ddr_cfg_regs
));
209 else if(ddr_freq_mhz
<= 667)
210 memcpy(&ddr_cfg_regs
, &ddr_cfg_regs_667
, sizeof(ddr_cfg_regs
));
211 else if(ddr_freq_mhz
<= 800)
212 memcpy(&ddr_cfg_regs
, &ddr_cfg_regs_800
, sizeof(ddr_cfg_regs
));
214 panic("Unsupported DDR data rate %s MT/s data rate\n",
215 strmhz(buf
, ddr_freq
));
217 /* P1020 and it's derivatives support max 32bit DDR width */
218 if (cpu
->soc_ver
== SVR_P1020
|| cpu
->soc_ver
== SVR_P1011
) {
219 ddr_cfg_regs
.ddr_sdram_cfg
|= SDRAM_CFG_32_BE
;
220 ddr_cfg_regs
.cs
[0].bnds
= 0x0000001F;
223 fsl_ddr_set_memctl_regs(&ddr_cfg_regs
, 0);
225 set_ddr_laws(0, ddr_size
, LAW_TRGT_IF_DDR_1
);