board/freescale/p1_p2_rdb/pci.c

   1 /*
   2  * Copyright 2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/immap_85xx.h>
  27 #include <asm/io.h>
  28 #include <asm/fsl_pci.h>
  29 #include <libfdt.h>
  30 #include <fdt_support.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #ifdef CONFIG_PCIE1
  35 static struct pci_controller pcie1_hose;
  36 #endif
  37
  38 #ifdef CONFIG_PCIE2
  39 static struct pci_controller pcie2_hose;
  40 #endif
  41
  42 void pci_init_board(void)
  43 {
  44         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  45         struct fsl_pci_info pci_info[2];
  46         u32 devdisr, pordevsr, io_sel;
  47         int first_free_busno = 0;
  48         int num = 0;
  49
  50         int pcie_ep, pcie_configured;
  51
  52         devdisr = in_be32(&gur->devdisr);
  53         pordevsr = in_be32(&gur->pordevsr);
  54         io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
  55
  56         debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
  57
  58         if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
  59                 printf ("    eTSEC2 is in sgmii mode.\n");
  60
  61         puts("\n");
  62 #ifdef CONFIG_PCIE2
  63         pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
  64
  65         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
  66                 SET_STD_PCIE_INFO(pci_info[num], 2);
  67                 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
  68                 printf("    PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
  69                                 pcie_ep ? "Endpoint" : "Root Complex",
  70                                 pci_info[num].regs);
  71                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
  72                                         &pcie2_hose, first_free_busno);
  73         } else {
  74                 printf ("    PCIE2: disabled\n");
  75         }
  76         puts("\n");
  77 #else
  78         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
  79 #endif
  80
  81 #ifdef CONFIG_PCIE1
  82         pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
  83
  84         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
  85                 SET_STD_PCIE_INFO(pci_info[num], 1);
  86                 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
  87                 printf("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
  88                                 pcie_ep ? "Endpoint" : "Root Complex",
  89                                 pci_info[num].regs);
  90                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
  91                                         &pcie1_hose, first_free_busno);
  92         } else {
  93                 printf ("    PCIE1: disabled\n");
  94         }
  95         puts("\n");
  96 #else
  97         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
  98 #endif
  99 }
 100
 101 void ft_pci_board_setup(void *blob)
 102 {
 103 /* According to h/w manual, PCIE2 is at lower address(0x9000)
 104  * than PCIE1(0xa000).
 105  * Hence PCIE2 is made to occupy the pci1 position in dts to
 106  * keep the addresses sorted there.
 107  * Generally the case with all FSL SOCs.
 108  */
 109 #ifdef CONFIG_PCIE2
 110         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 111 #endif
 112 #ifdef CONFIG_PCIE1
 113         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 114 #endif
 115 }