2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
9 #include <asm/immap_85xx.h>
10 #include <asm/processor.h>
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
14 #include <asm/fsl_law.h>
16 #ifdef CONFIG_SYS_DDR_RAW_TIMING
17 #if defined(CONFIG_P1020RDB_PROTO) || \
18 defined(CONFIG_P1021RDB) || \
19 defined(CONFIG_P1020UTM)
20 /* Micron MT41J256M8_187E */
21 dimm_params_t ddr_raw_timing
= {
23 .rank_density
= 1073741824u,
24 .capacity
= 1073741824u,
25 .primary_sdram_width
= 32,
31 .n_banks_per_sdram_device
= 8,
33 .burst_lengths_bitmask
= 0x0c,
36 .caslat_x
= 0x1e << 4, /* 5,6,7,8 */
47 .refresh_rate_ps
= 7800000,
50 #elif defined(CONFIG_P2020RDB)
51 /* Micron MT41J128M16_15E */
52 dimm_params_t ddr_raw_timing
= {
54 .rank_density
= 1073741824u,
55 .capacity
= 1073741824u,
56 .primary_sdram_width
= 64,
62 .n_banks_per_sdram_device
= 8,
64 .burst_lengths_bitmask
= 0x0c,
67 .caslat_x
= 0x7e << 4, /* 5,6,7,8,9,10 */
78 .refresh_rate_ps
= 7800000,
81 #elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD))
82 /* Micron MT41J512M8_187E */
83 dimm_params_t ddr_raw_timing
= {
85 .rank_density
= 1073741824u,
86 .capacity
= 2147483648u,
87 .primary_sdram_width
= 32,
93 .n_banks_per_sdram_device
= 8,
95 .burst_lengths_bitmask
= 0x0c,
98 .caslat_x
= 0x1e << 4, /* 5,6,7,8 */
109 .refresh_rate_ps
= 7800000,
112 #elif defined(CONFIG_P1020RDB_PC)
114 * Samsung K4B2G0846C-HCF8
115 * The following timing are for "downshift"
116 * i.e. to use CL9 part as CL7
117 * otherwise, tAA, tRCD, tRP will be 13500ps
118 * and tRC will be 49500ps
120 dimm_params_t ddr_raw_timing
= {
122 .rank_density
= 1073741824u,
123 .capacity
= 1073741824u,
124 .primary_sdram_width
= 32,
126 .registered_dimm
= 0,
130 .n_banks_per_sdram_device
= 8,
132 .burst_lengths_bitmask
= 0x0c,
135 .caslat_x
= 0x1e << 4, /* 5,6,7,8 */
146 .refresh_rate_ps
= 7800000,
149 #elif defined(CONFIG_P1024RDB) || \
150 defined(CONFIG_P1025RDB)
152 * Samsung K4B2G0846C-HCH9
153 * The following timing are for "downshift"
154 * i.e. to use CL9 part as CL7
155 * otherwise, tAA, tRCD, tRP will be 13500ps
156 * and tRC will be 49500ps
158 dimm_params_t ddr_raw_timing
= {
160 .rank_density
= 1073741824u,
161 .capacity
= 1073741824u,
162 .primary_sdram_width
= 32,
164 .registered_dimm
= 0,
168 .n_banks_per_sdram_device
= 8,
170 .burst_lengths_bitmask
= 0x0c,
173 .caslat_x
= 0x3e << 4, /* 5,6,7,8,9 */
184 .refresh_rate_ps
= 7800000,
188 #error Missing raw timing data for this board
191 int fsl_ddr_get_dimm_params(dimm_params_t
*pdimm
,
192 unsigned int controller_number
,
193 unsigned int dimm_number
)
195 const char dimm_model
[] = "Fixed DDR on board";
197 if ((controller_number
== 0) && (dimm_number
== 0)) {
198 memcpy(pdimm
, &ddr_raw_timing
, sizeof(dimm_params_t
));
199 memset(pdimm
->mpart
, 0, sizeof(pdimm
->mpart
));
200 memcpy(pdimm
->mpart
, dimm_model
, sizeof(dimm_model
) - 1);
205 #endif /* CONFIG_SYS_DDR_RAW_TIMING */
207 #ifdef CONFIG_SYS_DDR_CS0_BNDS
208 /* Fixed sdram init -- doesn't use serial presence detect. */
209 phys_size_t
fixed_sdram(void)
214 fsl_ddr_cfg_regs_t ddr_cfg_regs
= {
215 .cs
[0].bnds
= CONFIG_SYS_DDR_CS0_BNDS
,
216 .cs
[0].config
= CONFIG_SYS_DDR_CS0_CONFIG
,
217 .cs
[0].config_2
= CONFIG_SYS_DDR_CS0_CONFIG_2
,
218 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
219 .cs
[1].bnds
= CONFIG_SYS_DDR_CS1_BNDS
,
220 .cs
[1].config
= CONFIG_SYS_DDR_CS1_CONFIG
,
221 .cs
[1].config_2
= CONFIG_SYS_DDR_CS1_CONFIG_2
,
223 .timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
,
224 .timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
,
225 .timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
,
226 .timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
,
227 .ddr_sdram_cfg
= CONFIG_SYS_DDR_CONTROL
,
228 .ddr_sdram_cfg_2
= CONFIG_SYS_DDR_CONTROL_2
,
229 .ddr_sdram_mode
= CONFIG_SYS_DDR_MODE_1
,
230 .ddr_sdram_mode_2
= CONFIG_SYS_DDR_MODE_2
,
231 .ddr_sdram_md_cntl
= CONFIG_SYS_DDR_MODE_CONTROL
,
232 .ddr_sdram_interval
= CONFIG_SYS_DDR_INTERVAL
,
233 .ddr_data_init
= CONFIG_SYS_DDR_DATA_INIT
,
234 .ddr_sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL
,
235 .ddr_init_addr
= CONFIG_SYS_DDR_INIT_ADDR
,
236 .ddr_init_ext_addr
= CONFIG_SYS_DDR_INIT_EXT_ADDR
,
237 .timing_cfg_4
= CONFIG_SYS_DDR_TIMING_4
,
238 .timing_cfg_5
= CONFIG_SYS_DDR_TIMING_5
,
239 .ddr_zq_cntl
= CONFIG_SYS_DDR_ZQ_CONTROL
,
240 .ddr_wrlvl_cntl
= CONFIG_SYS_DDR_WRLVL_CONTROL
,
241 .ddr_sr_cntr
= CONFIG_SYS_DDR_SR_CNTR
,
242 .ddr_sdram_rcw_1
= CONFIG_SYS_DDR_RCW_1
,
243 .ddr_sdram_rcw_2
= CONFIG_SYS_DDR_RCW_2
246 get_sys_info(&sysinfo
);
247 printf("Configuring DDR for %s MT/s data rate\n",
248 strmhz(buf
, sysinfo
.freq_ddrbus
));
250 ddr_size
= CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;
252 fsl_ddr_set_memctl_regs(&ddr_cfg_regs
, 0, 0);
254 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE
,
255 ddr_size
, LAW_TRGT_IF_DDR_1
) < 0) {
256 printf("ERROR setting Local Access Windows for DDR\n");
264 void fsl_ddr_board_options(memctl_options_t
*popts
,
265 dimm_params_t
*pdimm
,
266 unsigned int ctrl_num
)
269 popts
->clk_adjust
= 6;
270 popts
->cpo_override
= 0x1f;
271 popts
->write_data_delay
= 2;
272 popts
->half_strength_driver_enable
= 1;
273 /* Write leveling override */
275 popts
->wrlvl_override
= 1;
276 popts
->wrlvl_sample
= 0xf;
277 popts
->wrlvl_start
= 0x8;
278 popts
->trwt_override
= 1;
281 if (pdimm
->primary_sdram_width
== 64)
282 popts
->data_bus_width
= 0;
283 else if (pdimm
->primary_sdram_width
== 32)
284 popts
->data_bus_width
= 1;
286 printf("Error in DDR bus width configuration!\n");
288 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
289 popts
->cs_local_opts
[i
].odt_rd_cfg
= FSL_DDR_ODT_NEVER
;
290 popts
->cs_local_opts
[i
].odt_wr_cfg
= FSL_DDR_ODT_CS
;