board/freescale/p1_twr/p1_twr.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <hwconfig.h>
  10 #include <pci.h>
  11 #include <i2c.h>
  12 #include <asm/processor.h>
  13 #include <asm/mmu.h>
  14 #include <asm/cache.h>
  15 #include <asm/immap_85xx.h>
  16 #include <asm/fsl_pci.h>
  17 #include <fsl_ddr_sdram.h>
  18 #include <asm/io.h>
  19 #include <asm/fsl_law.h>
  20 #include <asm/fsl_lbc.h>
  21 #include <asm/mp.h>
  22 #include <miiphy.h>
  23 #include <libfdt.h>
  24 #include <fdt_support.h>
  25 #include <fsl_mdio.h>
  26 #include <tsec.h>
  27 #include <ioports.h>
  28 #include <asm/fsl_serdes.h>
  29 #include <netdev.h>
  30
  31 #define SYSCLK_64       64000000
  32 #define SYSCLK_66       66666666
  33
  34 unsigned long get_board_sys_clk(ulong dummy)
  35 {
  36         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  37         par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
  38         unsigned int cpdat_val = 0;
  39
  40         /* Set-up up pin muxing based on board switch settings */
  41         cpdat_val = par_io[1].cpdat;
  42
  43         /* Check switch setting for SYSCLK select (PB3)  */
  44         if (cpdat_val & 0x10000000)
  45                 return SYSCLK_64;
  46         else
  47                 return SYSCLK_66;
  48
  49         return 0;
  50 }
  51
  52 #ifdef CONFIG_QE
  53
  54 #define PCA_IOPORT_I2C_ADDR             0x23
  55 #define PCA_IOPORT_OUTPUT_CMD           0x2
  56 #define PCA_IOPORT_CFG_CMD              0x6
  57
  58 const qe_iop_conf_t qe_iop_conf_tab[] = {
  59
  60 #ifdef CONFIG_TWR_P1025
  61         /* GPIO */
  62         {1,  0, 1, 0, 0},
  63         {1,  18, 1, 0, 0},
  64
  65         /* GPIO for switch options */
  66         {1,  2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
  67         {1,  3, 2, 0, 0}, /* SYS_CLK_SELECT */
  68         {1,  29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
  69         {1,  30, 2, 0, 0}, /* ETH_TDM_SEL */
  70
  71         /* QE_MUX_MDC */
  72         {1,  19, 1, 0, 1}, /* QE_MUX_MDC */
  73
  74         /* QE_MUX_MDIO */
  75         {1,  20, 3, 0, 1}, /* QE_MUX_MDIO */
  76
  77         /* UCC_1_MII */
  78         {0, 23, 2, 0, 2}, /* CLK12 */
  79         {0, 24, 2, 0, 1}, /* CLK9 */
  80         {0,  7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
  81         {0,  9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
  82         {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
  83         {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
  84         {0,  6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
  85         {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
  86         {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
  87         {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
  88         {0,  5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
  89         {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
  90         {0,  4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
  91         {0,  8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
  92         {0, 17, 2, 0, 2}, /* ENET1_CRS */
  93         {0, 16, 2, 0, 2}, /* ENET1_COL */
  94
  95         /* UCC_5_RMII */
  96         {1, 11, 2, 0, 1}, /* CLK13 */
  97         {1, 7,  1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
  98         {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
  99         {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
 100         {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
 101         {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
 102         {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
 103         {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
 104
 105         /* TDMA - clock option is configured in OS based on board setting */
 106         {1, 23, 2, 0, 2}, /* TDMA_TXD */
 107         {1, 25, 2, 0, 2}, /* TDMA_RXD */
 108         {1, 26, 1, 0, 2}, /* TDMA_SYNC */
 109 #endif
 110
 111         {0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
 112 };
 113 #endif
 114
 115 int board_early_init_f(void)
 116 {
 117         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 118
 119         setbits_be32(&gur->pmuxcr,
 120                         (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
 121
 122         /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
 123         clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
 124
 125         return 0;
 126 }
 127
 128 int checkboard(void)
 129 {
 130         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 131         u8 boot_status;
 132
 133         printf("Board: %s\n", CONFIG_BOARDNAME);
 134
 135         boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
 136         puts("rom_loc: ");
 137         if (boot_status == PORBMSR_ROMLOC_NOR)
 138                 puts("nor flash");
 139         else if (boot_status == PORBMSR_ROMLOC_SDHC)
 140                 puts("sd");
 141         else
 142                 puts("unknown");
 143         puts("\n");
 144
 145         return 0;
 146 }
 147
 148 #ifdef CONFIG_PCI
 149 void pci_init_board(void)
 150 {
 151         fsl_pcie_init_board(0);
 152 }
 153 #endif
 154
 155 int board_early_init_r(void)
 156 {
 157         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 158         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 159
 160         /*
 161          * Remap Boot flash region to caching-inhibited
 162          * so that flash can be erased properly.
 163          */
 164
 165         /* Flush d-cache and invalidate i-cache of any FLASH data */
 166         flush_dcache();
 167         invalidate_icache();
 168
 169         if (flash_esel == -1) {
 170                 /* very unlikely unless something is messed up */
 171                 puts("Error: Could not find TLB for FLASH BASE\n");
 172                 flash_esel = 2; /* give our best effort to continue */
 173         } else {
 174                 /* invalidate existing TLB entry for flash */
 175                 disable_tlb(flash_esel);
 176         }
 177
 178         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
 179                 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,           /* perms, wimge */
 180                 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
 181         return 0;
 182 }
 183
 184 int board_eth_init(bd_t *bis)
 185 {
 186         struct fsl_pq_mdio_info mdio_info;
 187         struct tsec_info_struct tsec_info[4];
 188         ccsr_gur_t *gur __attribute__((unused)) =
 189                 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 190         int num = 0;
 191
 192 #ifdef CONFIG_TSEC1
 193         SET_STD_TSEC_INFO(tsec_info[num], 1);
 194         num++;
 195 #endif
 196 #ifdef CONFIG_TSEC2
 197         SET_STD_TSEC_INFO(tsec_info[num], 2);
 198         if (is_serdes_configured(SGMII_TSEC2)) {
 199                 printf("eTSEC2 is in sgmii mode.\n");
 200                 tsec_info[num].flags |= TSEC_SGMII;
 201         }
 202         num++;
 203 #endif
 204 #ifdef CONFIG_TSEC3
 205         SET_STD_TSEC_INFO(tsec_info[num], 3);
 206         num++;
 207 #endif
 208
 209         if (!num) {
 210                 printf("No TSECs initialized\n");
 211                 return 0;
 212         }
 213
 214         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 215         mdio_info.name = DEFAULT_MII_NAME;
 216
 217         fsl_pq_mdio_init(bis, &mdio_info);
 218
 219         tsec_eth_init(bis, tsec_info, num);
 220
 221 #if defined(CONFIG_UEC_ETH)
 222         /* QE0 and QE3 need to be exposed for UCC1
 223          * and UCC5 Eth mode (in PMUXCR register).
 224          * Currently QE/LBC muxed pins assumed to be
 225          * LBC for U-Boot and PMUXCR updated by OS if required */
 226
 227         uec_standard_init(bis);
 228 #endif
 229
 230         return pci_eth_init(bis);
 231 }
 232
 233 #if defined(CONFIG_QE)
 234 static void fdt_board_fixup_qe_pins(void *blob)
 235 {
 236         int node;
 237
 238         if (!hwconfig("qe")) {
 239                 /* For QE and eLBC pins multiplexing,
 240                  * When don't use QE function, remove
 241                  * qe node from dt blob.
 242                  */
 243                 node = fdt_path_offset(blob, "/qe");
 244                 if (node >= 0)
 245                         fdt_del_node(blob, node);
 246         } else {
 247                 /* For TWR Peripheral Modules - TWR-SER2
 248                  * board only can support Signal Port MII,
 249                  * so delete one UEC node when use MII port.
 250                  */
 251                 if (hwconfig("mii"))
 252                         node = fdt_path_offset(blob, "/qe/ucc@2400");
 253                 else
 254                         node = fdt_path_offset(blob, "/qe/ucc@2000");
 255                 if (node >= 0)
 256                         fdt_del_node(blob, node);
 257         }
 258
 259         return;
 260 }
 261 #endif
 262
 263 #ifdef CONFIG_OF_BOARD_SETUP
 264 int ft_board_setup(void *blob, bd_t *bd)
 265 {
 266         phys_addr_t base;
 267         phys_size_t size;
 268
 269         ft_cpu_setup(blob, bd);
 270
 271         base = getenv_bootm_low();
 272         size = getenv_bootm_size();
 273
 274         fdt_fixup_memory(blob, (u64)base, (u64)size);
 275
 276         FT_FSL_PCI_SETUP;
 277
 278 #ifdef CONFIG_QE
 279         do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
 280                         sizeof("okay"), 0);
 281 #endif
 282 #if defined(CONFIG_TWR_P1025)
 283         fdt_board_fixup_qe_pins(blob);
 284 #endif
 285         fsl_fdt_fixup_dr_usb(blob, bd);
 286
 287         return 0;
 288 }
 289 #endif