2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 struct fsl_e_tlb_entry tlb_table
[] = {
11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
,
13 CONFIG_SYS_INIT_RAM_ADDR_PHYS
,
15 0, 0, BOOKE_PAGESZ_4K
, 0),
16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 4 * 1024 ,
17 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 4 * 1024,
19 0, 0, BOOKE_PAGESZ_4K
, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 8 * 1024 ,
21 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 8 * 1024,
23 0, 0, BOOKE_PAGESZ_4K
, 0),
24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 12 * 1024 ,
25 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 12 * 1024,
27 0, 0, BOOKE_PAGESZ_4K
, 0),
30 /* *I*** - Covers boot page */
31 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
32 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
33 0, 0, BOOKE_PAGESZ_4K
, 1),
36 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR
, CONFIG_SYS_CCSRBAR_PHYS
,
37 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
38 0, 1, BOOKE_PAGESZ_1M
, 1),
40 #if defined(CONFIG_PCI)
41 /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
42 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT
, CONFIG_SYS_PCIE3_MEM_PHYS
,
43 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
44 0, 2, BOOKE_PAGESZ_1G
, 1),
46 /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
47 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT
, CONFIG_SYS_PCIE1_MEM_VIRT
,
48 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
49 0, 3, BOOKE_PAGESZ_256M
, 1),
51 /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */
52 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT
+ 0x10000000,
53 CONFIG_SYS_PCIE1_MEM_PHYS
+ 0x10000000,
54 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
55 0, 4, BOOKE_PAGESZ_256M
, 1),
64 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT
, CONFIG_SYS_PCIE3_IO_PHYS
,
65 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
66 0, 5, BOOKE_PAGESZ_256K
, 1),
67 #endif /* #if defined(CONFIG_PCI) */
69 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
70 /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */
71 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR
, CONFIG_SYS_INIT_L2_ADDR_PHYS
,
72 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
73 0, 6, BOOKE_PAGESZ_256K
, 1),
75 /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
76 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR
+ 0x40000,
77 CONFIG_SYS_INIT_L2_ADDR_PHYS
+ 0x40000,
78 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
79 0, 7, BOOKE_PAGESZ_256K
, 1),
83 int num_tlb_entries
= ARRAY_SIZE(tlb_table
);