board/freescale/p2041rdb/p2041rdb.c

   1 /*
   2  * Copyright 2011,2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <netdev.h>
  10 #include <linux/compiler.h>
  11 #include <asm/mmu.h>
  12 #include <asm/processor.h>
  13 #include <asm/cache.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_liodn.h>
  18 #include <fm_eth.h>
  19
  20 extern void pci_of_setup(void *blob, bd_t *bd);
  21
  22 #include "cpld.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 int checkboard(void)
  27 {
  28         u8 sw;
  29         struct cpu_type *cpu = gd->arch.cpu;
  30         unsigned int i;
  31
  32         printf("Board: %sRDB, ", cpu->name);
  33         printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
  34                         CPLD_READ(cpld_ver_sub));
  35
  36         sw = CPLD_READ(fbank_sel);
  37         printf("vBank: %d\n", sw & 0x1);
  38
  39         /*
  40          * Display the actual SERDES reference clocks as configured by the
  41          * dip switches on the board.  Note that the SWx registers could
  42          * technically be set to force the reference clocks to match the
  43          * values that the SERDES expects (or vice versa).  For now, however,
  44          * we just display both values and hope the user notices when they
  45          * don't match.
  46          */
  47         puts("SERDES Reference Clocks: ");
  48         sw = in_8(&CPLD_SW(2)) >> 2;
  49         for (i = 0; i < 2; i++) {
  50                 static const char * const freq[][3] = {{"0", "100", "125"},
  51                                                 {"100", "156.25", "125"}
  52                 };
  53                 unsigned int clock = (sw >> (2 * i)) & 3;
  54
  55                 printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
  56         }
  57         puts("\n");
  58
  59         return 0;
  60 }
  61
  62 int board_early_init_f(void)
  63 {
  64         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  65
  66         /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
  67         setbits_be32(&gur->ddrclkdr, 0x000f000f);
  68
  69         return 0;
  70 }
  71
  72 #define CPLD_LANE_A_SEL 0x1
  73 #define CPLD_LANE_G_SEL 0x2
  74 #define CPLD_LANE_C_SEL 0x4
  75 #define CPLD_LANE_D_SEL 0x8
  76
  77 void board_config_lanes_mux(void)
  78 {
  79         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  80         int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
  81                                 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
  82
  83         u8 mux = 0;
  84         switch (srds_prtcl) {
  85         case 0x2:
  86         case 0x5:
  87         case 0x9:
  88         case 0xa:
  89         case 0xf:
  90                 break;
  91         case 0x8:
  92                 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
  93                 break;
  94         case 0x14:
  95                 mux |= CPLD_LANE_A_SEL;
  96                 break;
  97         case 0x17:
  98                 mux |= CPLD_LANE_G_SEL;
  99                 break;
 100         case 0x16:
 101         case 0x19:
 102         case 0x1a:
 103                 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
 104                 break;
 105         case 0x1c:
 106                 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
 107                 break;
 108         default:
 109                 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
 110                 break;
 111         }
 112         CPLD_WRITE(serdes_mux, mux);
 113 }
 114
 115 int board_early_init_r(void)
 116 {
 117         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 118         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 119
 120         /*
 121          * Remap Boot flash + PROMJET region to caching-inhibited
 122          * so that flash can be erased properly.
 123          */
 124
 125         /* Flush d-cache and invalidate i-cache of any FLASH data */
 126         flush_dcache();
 127         invalidate_icache();
 128
 129         if (flash_esel == -1) {
 130                 /* very unlikely unless something is messed up */
 131                 puts("Error: Could not find TLB for FLASH BASE\n");
 132                 flash_esel = 2; /* give our best effort to continue */
 133         } else {
 134                 /* invalidate existing TLB entry for flash + promjet */
 135                 disable_tlb(flash_esel);
 136         }
 137
 138         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 139                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 140                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 141
 142         board_config_lanes_mux();
 143
 144         return 0;
 145 }
 146
 147 unsigned long get_board_sys_clk(unsigned long dummy)
 148 {
 149         u8 sysclk_conf = CPLD_READ(sysclk_sw1);
 150
 151         switch (sysclk_conf & 0x7) {
 152         case CPLD_SYSCLK_83:
 153                 return 83333333;
 154         case CPLD_SYSCLK_100:
 155                 return 100000000;
 156         default:
 157                 return 66666666;
 158         }
 159 }
 160
 161 #define NUM_SRDS_BANKS  2
 162
 163 int misc_init_r(void)
 164 {
 165         serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 166         u32 actual[NUM_SRDS_BANKS];
 167         unsigned int i;
 168         u8 sw;
 169         static const int freq[][3] = {
 170                 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
 171                 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
 172                         SRDS_PLLCR0_RFCK_SEL_125}
 173         };
 174
 175         sw = in_8(&CPLD_SW(2)) >> 2;
 176         for (i = 0; i < NUM_SRDS_BANKS; i++) {
 177                 unsigned int clock = (sw >> (2 * i)) & 3;
 178                 if (clock == 0x3) {
 179                         printf("Warning: SDREFCLK%u switch setting of '11' is "
 180                                "unsupported\n", i + 1);
 181                         break;
 182                 }
 183                 if (i == 0 && clock == 0)
 184                         puts("Warning: SDREFCLK1 switch setting of"
 185                                 "'00' is unsupported\n");
 186                 else
 187                         actual[i] = freq[i][clock];
 188
 189                 /*
 190                  * PC board uses a different CPLD with PB board, this CPLD
 191                  * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
 192                  * board has cpld_ver_sub = 0, and pcba_ver = 4.
 193                  */
 194                 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
 195                     (CPLD_READ(pcba_ver) == 5)) {
 196                         /* PC board bank2 frequency */
 197                         actual[i] = freq[i-1][clock];
 198                 }
 199         }
 200
 201         for (i = 0; i < NUM_SRDS_BANKS; i++) {
 202                 u32 expected = in_be32(&regs->bank[i].pllcr0);
 203                 expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
 204                 if (expected != actual[i]) {
 205                         printf("Warning: SERDES bank %u expects reference clock"
 206                                " %sMHz, but actual is %sMHz\n", i + 1,
 207                                serdes_clock_to_string(expected),
 208                                serdes_clock_to_string(actual[i]));
 209                 }
 210         }
 211
 212         return 0;
 213 }
 214
 215 int ft_board_setup(void *blob, bd_t *bd)
 216 {
 217         phys_addr_t base;
 218         phys_size_t size;
 219
 220         ft_cpu_setup(blob, bd);
 221
 222         base = getenv_bootm_low();
 223         size = getenv_bootm_size();
 224
 225         fdt_fixup_memory(blob, (u64)base, (u64)size);
 226
 227 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 228         fsl_fdt_fixup_dr_usb(blob, bd);
 229 #endif
 230
 231 #ifdef CONFIG_PCI
 232         pci_of_setup(blob, bd);
 233 #endif
 234
 235         fdt_fixup_liodn(blob);
 236 #ifdef CONFIG_SYS_DPAA_FMAN
 237         fdt_fixup_fman_ethernet(blob);
 238 #endif
 239
 240         return 0;
 241 }