2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_liodn.h>
21 #include "../common/qixis.h"
23 #include "t102xqds_qixis.h"
24 #include "../common/sleep.h"
26 DECLARE_GLOBAL_DATA_PTR
;
31 struct cpu_type
*cpu
= gd
->arch
.cpu
;
32 static const char *const freq
[] = {"100", "125", "156.25", "100.0"};
34 u8 sw
= QIXIS_READ(arch
);
36 printf("Board: %sQDS, ", cpu
->name
);
37 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id
), sw
>> 4);
38 printf("Board Version: %c, boot from ", (sw
& 0xf) + 'A' - 1);
45 sw
= QIXIS_READ(brdcfg
[0]);
46 sw
= (sw
& QIXIS_LBMAP_MASK
) >> QIXIS_LBMAP_SHIFT
;
49 printf("vBank: %d\n", sw
);
57 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH
);
60 printf("FPGA: v%d (%s), build %d",
61 (int)QIXIS_READ(scver
), qixis_read_tag(buf
),
62 (int)qixis_read_minor());
63 /* the timestamp string contains "\n" at the end */
64 printf(" on %s", qixis_read_time(buf
));
66 puts("SERDES Reference: ");
67 sw
= QIXIS_READ(brdcfg
[2]);
68 clock
= (sw
>> 6) & 3;
69 printf("Clock1=%sMHz ", freq
[clock
]);
70 clock
= (sw
>> 4) & 3;
71 printf("Clock2=%sMHz\n", freq
[clock
]);
76 int select_i2c_ch_pca9547(u8 ch
)
80 ret
= i2c_write(I2C_MUX_PCA_ADDR_PRI
, 0, 1, &ch
, 1);
82 puts("PCA: failed to select proper channel\n");
89 static int board_mux_lane_to_slot(void)
91 ccsr_gur_t __iomem
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
95 srds_prtcl_s1
= in_be32(&gur
->rcwsr
[4]) &
96 FSL_CORENET2_RCWSR4_SRDS1_PRTCL
;
97 srds_prtcl_s1
>>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT
;
100 brdcfg9
= QIXIS_READ(brdcfg
[9]);
101 QIXIS_WRITE(brdcfg
[9], brdcfg9
| BRDCFG9_XFI_TX_DISABLE
);
103 switch (srds_prtcl_s1
) {
105 /* SerDes1 is not enabled */
113 QIXIS_WRITE(brdcfg
[12], 0x8c);
116 QIXIS_WRITE(brdcfg
[12], 0xfc);
122 QIXIS_WRITE(brdcfg
[12], 0x88);
125 QIXIS_WRITE(brdcfg
[12], 0xcc);
128 QIXIS_WRITE(brdcfg
[12], 0xc8);
132 brdcfg9
&= ~BRDCFG9_XFI_TX_DISABLE
;
133 QIXIS_WRITE(brdcfg
[9], brdcfg9
);
134 QIXIS_WRITE(brdcfg
[12], 0x8c);
137 QIXIS_WRITE(brdcfg
[12], 0x00);
143 /* Aurora, PCIe, SGMII, SATA */
144 QIXIS_WRITE(brdcfg
[12], 0x04);
147 printf("WARNING: unsupported for SerDes Protocol %d\n",
155 #ifdef CONFIG_ARCH_T1024
156 static void board_mux_setup(void)
160 brdcfg15
= QIXIS_READ(brdcfg
[15]);
161 brdcfg15
&= ~BRDCFG15_DIUSEL_MASK
;
163 if (hwconfig_arg_cmp("pin_mux", "tdm")) {
164 /* Route QE_TDM multiplexed signals to TDM Riser slot */
165 QIXIS_WRITE(brdcfg
[15], brdcfg15
| BRDCFG15_DIUSEL_TDM
);
166 QIXIS_WRITE(brdcfg
[13], BRDCFG13_TDM_INTERFACE
<< 2);
167 QIXIS_WRITE(brdcfg
[5], (QIXIS_READ(brdcfg
[5]) &
168 ~BRDCFG5_SPIRTE_MASK
) | BRDCFG5_SPIRTE_TDM
);
169 } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
170 /* to UCC (ProfiBus) interface */
171 QIXIS_WRITE(brdcfg
[15], brdcfg15
| BRDCFG15_DIUSEL_UCC
);
172 } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
173 /* to DVI (HDMI) encoder */
174 QIXIS_WRITE(brdcfg
[15], brdcfg15
| BRDCFG15_DIUSEL_HDMI
);
175 } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
176 /* to DFP (LCD) encoder */
177 QIXIS_WRITE(brdcfg
[15], brdcfg15
| BRDCFG15_LCDFM
|
178 BRDCFG15_LCDPD
| BRDCFG15_DIUSEL_LCD
);
181 if (hwconfig_arg_cmp("adaptor", "sdxc"))
182 /* Route SPI_CS multiplexed signals to SD slot */
183 QIXIS_WRITE(brdcfg
[5], (QIXIS_READ(brdcfg
[5]) &
184 ~BRDCFG5_SPIRTE_MASK
) | BRDCFG5_SPIRTE_SDHC
);
188 void board_retimer_ds125df111_init(void)
192 /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
194 i2c_write(I2C_MUX_PCA_ADDR_PRI
, 0, 1, ®
, 1);
196 i2c_write(I2C_MUX_PCA_ADDR_SEC
, 0, 1, ®
, 1);
198 /* Access to Control/Shared register */
200 i2c_write(I2C_RETIMER_ADDR
, 0xff, 1, ®
, 1);
202 /* Read device revision and ID */
203 i2c_read(I2C_RETIMER_ADDR
, 1, 1, ®
, 1);
204 debug("Retimer version id = 0x%x\n", reg
);
206 /* Enable Broadcast */
208 i2c_write(I2C_RETIMER_ADDR
, 0xff, 1, ®
, 1);
210 /* Reset Channel Registers */
211 i2c_read(I2C_RETIMER_ADDR
, 0, 1, ®
, 1);
213 i2c_write(I2C_RETIMER_ADDR
, 0, 1, ®
, 1);
215 /* Enable override divider select and Enable Override Output Mux */
216 i2c_read(I2C_RETIMER_ADDR
, 9, 1, ®
, 1);
218 i2c_write(I2C_RETIMER_ADDR
, 9, 1, ®
, 1);
220 /* Select VCO Divider to full rate (000) */
221 i2c_read(I2C_RETIMER_ADDR
, 0x18, 1, ®
, 1);
223 i2c_write(I2C_RETIMER_ADDR
, 0x18, 1, ®
, 1);
225 /* Select active PFD MUX input as re-timed data (001) */
226 i2c_read(I2C_RETIMER_ADDR
, 0x1e, 1, ®
, 1);
229 i2c_write(I2C_RETIMER_ADDR
, 0x1e, 1, ®
, 1);
231 /* Set data rate as 10.3125 Gbps */
233 i2c_write(I2C_RETIMER_ADDR
, 0x60, 1, ®
, 1);
235 i2c_write(I2C_RETIMER_ADDR
, 0x61, 1, ®
, 1);
237 i2c_write(I2C_RETIMER_ADDR
, 0x62, 1, ®
, 1);
239 i2c_write(I2C_RETIMER_ADDR
, 0x63, 1, ®
, 1);
241 i2c_write(I2C_RETIMER_ADDR
, 0x64, 1, ®
, 1);
244 int board_early_init_f(void)
246 #if defined(CONFIG_DEEP_SLEEP)
248 fsl_dp_disable_console();
254 int board_early_init_r(void)
256 #ifdef CONFIG_SYS_FLASH_BASE
257 const unsigned int flashbase
= CONFIG_SYS_FLASH_BASE
;
258 int flash_esel
= find_tlb_idx((void *)flashbase
, 1);
261 * Remap Boot flash + PROMJET region to caching-inhibited
262 * so that flash can be erased properly.
265 /* Flush d-cache and invalidate i-cache of any FLASH data */
269 if (flash_esel
== -1) {
270 /* very unlikely unless something is messed up */
271 puts("Error: Could not find TLB for FLASH BASE\n");
272 flash_esel
= 2; /* give our best effort to continue */
274 /* invalidate existing TLB entry for flash + promjet */
275 disable_tlb(flash_esel
);
278 set_tlb(1, flashbase
, CONFIG_SYS_FLASH_BASE_PHYS
,
279 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
280 0, flash_esel
, BOOKE_PAGESZ_256M
, 1);
282 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT
);
283 board_mux_lane_to_slot();
284 board_retimer_ds125df111_init();
286 /* Increase IO drive strength to address FCS error on RGMII */
287 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR
, 0xbfdb7800);
292 unsigned long get_board_sys_clk(void)
294 u8 sysclk_conf
= QIXIS_READ(brdcfg
[1]);
296 switch (sysclk_conf
& 0x0F) {
297 case QIXIS_SYSCLK_64
:
299 case QIXIS_SYSCLK_83
:
301 case QIXIS_SYSCLK_100
:
303 case QIXIS_SYSCLK_125
:
305 case QIXIS_SYSCLK_133
:
307 case QIXIS_SYSCLK_150
:
309 case QIXIS_SYSCLK_160
:
311 case QIXIS_SYSCLK_166
:
317 unsigned long get_board_ddr_clk(void)
319 u8 ddrclk_conf
= QIXIS_READ(brdcfg
[1]);
321 switch ((ddrclk_conf
& 0x30) >> 4) {
322 case QIXIS_DDRCLK_100
:
324 case QIXIS_DDRCLK_125
:
326 case QIXIS_DDRCLK_133
:
332 #define NUM_SRDS_PLL 2
333 int misc_init_r(void)
335 #ifdef CONFIG_ARCH_T1024
341 void fdt_fixup_spi_mux(void *blob
)
345 if (hwconfig_arg_cmp("pin_mux", "tdm")) {
346 while ((nodeoff
= fdt_node_offset_by_compatible(blob
, 0,
347 "eon,en25s64")) >= 0) {
348 fdt_del_node(blob
, nodeoff
);
351 /* remove tdm node */
352 while ((nodeoff
= fdt_node_offset_by_compatible(blob
, 0,
353 "maxim,ds26522")) >= 0) {
354 fdt_del_node(blob
, nodeoff
);
359 int ft_board_setup(void *blob
, bd_t
*bd
)
364 ft_cpu_setup(blob
, bd
);
366 base
= getenv_bootm_low();
367 size
= getenv_bootm_size();
369 fdt_fixup_memory(blob
, (u64
)base
, (u64
)size
);
372 pci_of_setup(blob
, bd
);
375 fdt_fixup_liodn(blob
);
377 #ifdef CONFIG_HAS_FSL_DR_USB
378 fsl_fdt_fixup_dr_usb(blob
, bd
);
381 #ifdef CONFIG_SYS_DPAA_FMAN
382 fdt_fixup_fman_ethernet(blob
);
383 fdt_fixup_board_enet(blob
);
385 fdt_fixup_spi_mux(blob
);
390 void qixis_dump_switch(void)
394 QIXIS_WRITE(cms
[0], 0x00);
395 nr_of_cfgsw
= QIXIS_READ(cms
[1]);
397 puts("DIP switch settings dump:\n");
398 for (i
= 1; i
<= nr_of_cfgsw
; i
++) {
399 QIXIS_WRITE(cms
[0], i
);
400 printf("SW%d = (0x%02x)\n", i
, QIXIS_READ(cms
[1]));