board/freescale/t102xrdb/t102xrdb.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <i2c.h>
  10 #include <netdev.h>
  11 #include <linux/compiler.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_liodn.h>
  18 #include <fm_eth.h>
  19 #include "t102xrdb.h"
  20 #ifdef CONFIG_TARGET_T1024RDB
  21 #include "cpld.h"
  22 #elif defined(CONFIG_TARGET_T1023RDB)
  23 #include <i2c.h>
  24 #include <mmc.h>
  25 #endif
  26 #include "../common/sleep.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #ifdef CONFIG_TARGET_T1023RDB
  31 enum {
  32         GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
  33         GPIO1_EMMC_SEL,
  34         GPIO3_GET_VERSION,             /* GPIO3_4/5, 00:RevB, 01: RevC */
  35         GPIO3_BRD_VER_MASK = 0x0c000000,
  36         GPIO3_OFFSET = 0x2000,
  37         I2C_GET_BANK,
  38         I2C_SET_BANK0,
  39         I2C_SET_BANK4,
  40 };
  41 #endif
  42
  43 int checkboard(void)
  44 {
  45         struct cpu_type *cpu = gd->arch.cpu;
  46         static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
  47         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  48         u32 srds_s1;
  49
  50         srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  51         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  52
  53         printf("Board: %sRDB, ", cpu->name);
  54 #if defined(CONFIG_TARGET_T1024RDB)
  55         printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  56                CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  57 #elif defined(CONFIG_TARGET_T1023RDB)
  58         printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
  59 #endif
  60         printf("boot from ");
  61
  62 #ifdef CONFIG_SDCARD
  63         puts("SD/MMC\n");
  64 #elif CONFIG_SPIFLASH
  65         puts("SPI\n");
  66 #elif defined(CONFIG_TARGET_T1024RDB)
  67         u8 reg;
  68
  69         reg = CPLD_READ(flash_csr);
  70
  71         if (reg & CPLD_BOOT_SEL) {
  72                 puts("NAND\n");
  73         } else {
  74                 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  75                 printf("NOR vBank%d\n", reg);
  76         }
  77 #elif defined(CONFIG_TARGET_T1023RDB)
  78 #ifdef CONFIG_NAND
  79         puts("NAND\n");
  80 #else
  81         printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
  82 #endif
  83 #endif
  84
  85         puts("SERDES Reference Clocks:\n");
  86         if (srds_s1 == 0x95)
  87                 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
  88         else
  89                 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
  90
  91         return 0;
  92 }
  93
  94 #ifdef CONFIG_TARGET_T1024RDB
  95 static void board_mux_lane(void)
  96 {
  97         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  98         u32 srds_prtcl_s1;
  99         u8 reg = CPLD_READ(misc_ctl_status);
 100
 101         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 102                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 103         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 104
 105         if (srds_prtcl_s1 == 0x95) {
 106                 /* Route Lane B to PCIE */
 107                 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
 108         } else {
 109                 /* Route Lane B to SGMII */
 110                 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
 111         }
 112         CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
 113 }
 114 #endif
 115
 116 int board_early_init_f(void)
 117 {
 118 #if defined(CONFIG_DEEP_SLEEP)
 119         if (is_warm_boot())
 120                 fsl_dp_disable_console();
 121 #endif
 122
 123         return 0;
 124 }
 125
 126 int board_early_init_r(void)
 127 {
 128 #ifdef CONFIG_SYS_FLASH_BASE
 129         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 130         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 131         /*
 132          * Remap Boot flash region to caching-inhibited
 133          * so that flash can be erased properly.
 134          */
 135
 136         /* Flush d-cache and invalidate i-cache of any FLASH data */
 137         flush_dcache();
 138         invalidate_icache();
 139         if (flash_esel == -1) {
 140                 /* very unlikely unless something is messed up */
 141                 puts("Error: Could not find TLB for FLASH BASE\n");
 142                 flash_esel = 2; /* give our best effort to continue */
 143         } else {
 144                 /* invalidate existing TLB entry for flash + promjet */
 145                 disable_tlb(flash_esel);
 146         }
 147
 148         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 149                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 150                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 151 #endif
 152
 153 #ifdef CONFIG_TARGET_T1024RDB
 154         board_mux_lane();
 155 #endif
 156
 157         return 0;
 158 }
 159
 160 unsigned long get_board_sys_clk(void)
 161 {
 162         return CONFIG_SYS_CLK_FREQ;
 163 }
 164
 165 unsigned long get_board_ddr_clk(void)
 166 {
 167         return CONFIG_DDR_CLK_FREQ;
 168 }
 169
 170 #ifdef CONFIG_TARGET_T1024RDB
 171 void board_reset(void)
 172 {
 173         CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
 174 }
 175 #endif
 176
 177 int misc_init_r(void)
 178 {
 179         return 0;
 180 }
 181
 182 int ft_board_setup(void *blob, bd_t *bd)
 183 {
 184         phys_addr_t base;
 185         phys_size_t size;
 186
 187         ft_cpu_setup(blob, bd);
 188
 189         base = env_get_bootm_low();
 190         size = env_get_bootm_size();
 191
 192         fdt_fixup_memory(blob, (u64)base, (u64)size);
 193
 194 #ifdef CONFIG_PCI
 195         pci_of_setup(blob, bd);
 196 #endif
 197
 198         fdt_fixup_liodn(blob);
 199         fsl_fdt_fixup_dr_usb(blob, bd);
 200
 201 #ifdef CONFIG_SYS_DPAA_FMAN
 202         fdt_fixup_fman_ethernet(blob);
 203         fdt_fixup_board_enet(blob);
 204 #endif
 205
 206 #ifdef CONFIG_TARGET_T1023RDB
 207         if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
 208                 fdt_enable_nor(blob);
 209 #endif
 210
 211         return 0;
 212 }
 213
 214 #ifdef CONFIG_TARGET_T1023RDB
 215 /* Enable NOR flash for RevC */
 216 static void fdt_enable_nor(void *blob)
 217 {
 218         int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
 219
 220         if (nodeoff >= 0)
 221                 fdt_status_okay(blob, nodeoff);
 222         else
 223                 printf("WARNING unable to set status for NOR\n");
 224 }
 225
 226 int board_mmc_getcd(struct mmc *mmc)
 227 {
 228         ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 229         u32 val = in_be32(&pgpio->gpdat);
 230
 231         /* GPIO1_14, 0: eMMC, 1: SD/MMC */
 232         val &= GPIO1_SD_SEL;
 233
 234         return val ? -1 : 1;
 235 }
 236
 237 int board_mmc_getwp(struct mmc *mmc)
 238 {
 239         ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 240         u32 val = in_be32(&pgpio->gpdat);
 241
 242         val &= GPIO1_SD_SEL;
 243
 244         return val ? -1 : 0;
 245 }
 246
 247 static u32 t1023rdb_ctrl(u32 ctrl_type)
 248 {
 249         ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 250         ccsr_gur_t __iomem  *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 251         u32 val, orig_bus = i2c_get_bus_num();
 252         u8 tmp;
 253
 254         switch (ctrl_type) {
 255         case GPIO1_SD_SEL:
 256                 val = in_be32(&pgpio->gpdat);
 257                 val |= GPIO1_SD_SEL;
 258                 out_be32(&pgpio->gpdat, val);
 259                 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 260                 break;
 261         case GPIO1_EMMC_SEL:
 262                 val = in_be32(&pgpio->gpdat);
 263                 val &= ~GPIO1_SD_SEL;
 264                 out_be32(&pgpio->gpdat, val);
 265                 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 266                 break;
 267         case GPIO3_GET_VERSION:
 268                 pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
 269                          + GPIO3_OFFSET);
 270                 val = in_be32(&pgpio->gpdat);
 271                 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
 272                 if (val == 0x3) /* GPIO3_4/5 not used on RevB */
 273                         val = 0;
 274                 return val;
 275         case I2C_GET_BANK:
 276                 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
 277                 i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
 278                 tmp &= 0x7;
 279                 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
 280                 i2c_set_bus_num(orig_bus);
 281                 return tmp;
 282         case I2C_SET_BANK0:
 283                 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
 284                 tmp = 0x0;
 285                 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
 286                 tmp = 0xf8;
 287                 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
 288                 /* asserting HRESET_REQ */
 289                 out_be32(&gur->rstcr, 0x2);
 290                 break;
 291         case I2C_SET_BANK4:
 292                 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
 293                 tmp = 0x1;
 294                 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
 295                 tmp = 0xf8;
 296                 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
 297                 out_be32(&gur->rstcr, 0x2);
 298                 break;
 299         default:
 300                 break;
 301         }
 302         return 0;
 303 }
 304
 305 static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 306                     char * const argv[])
 307 {
 308         if (argc < 2)
 309                 return CMD_RET_USAGE;
 310         if (!strcmp(argv[1], "bank0"))
 311                 t1023rdb_ctrl(I2C_SET_BANK0);
 312         else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
 313                 t1023rdb_ctrl(I2C_SET_BANK4);
 314         else if (!strcmp(argv[1], "sd"))
 315                 t1023rdb_ctrl(GPIO1_SD_SEL);
 316         else if (!strcmp(argv[1], "emmc"))
 317                 t1023rdb_ctrl(GPIO1_EMMC_SEL);
 318         else
 319                 return CMD_RET_USAGE;
 320         return 0;
 321 }
 322
 323 U_BOOT_CMD(
 324         switch, 2, 0, switch_cmd,
 325         "for bank0/bank4/sd/emmc switch control in runtime",
 326         "command (e.g. switch bank4)"
 327 );
 328 #endif