board/freescale/t102xrdb/t102xrdb.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <i2c.h>
  10 #include <netdev.h>
  11 #include <linux/compiler.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <fm_eth.h>
  20 #include "t102xrdb.h"
  21 #ifdef CONFIG_T1024RDB
  22 #include "cpld.h"
  23 #endif
  24 #include "../common/sleep.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #ifdef CONFIG_T1023RDB
  29 enum {
  30         GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */
  31         GPIO1_EMMC_SEL,
  32         GPIO1_VBANK0,
  33         GPIO1_VBANK4    = 0x00008000, /* GPIO1_16/20/22,  100:vBank4 */
  34         GPIO1_VBANK_MASK = 0x00008a00,
  35         GPIO1_DIR_OUTPUT = 0x00028a00,
  36         GPIO1_GET_VAL,
  37 };
  38 #endif
  39
  40 int checkboard(void)
  41 {
  42         struct cpu_type *cpu = gd->arch.cpu;
  43         static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
  44         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  45         u32 srds_s1;
  46
  47         srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  48         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  49
  50         printf("Board: %sRDB, ", cpu->name);
  51 #ifdef CONFIG_T1024RDB
  52         printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  53                CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  54 #endif
  55         printf("boot from ");
  56
  57 #ifdef CONFIG_SDCARD
  58         puts("SD/MMC\n");
  59 #elif CONFIG_SPIFLASH
  60         puts("SPI\n");
  61 #elif defined(CONFIG_T1024RDB)
  62         u8 reg;
  63
  64         reg = CPLD_READ(flash_csr);
  65
  66         if (reg & CPLD_BOOT_SEL) {
  67                 puts("NAND\n");
  68         } else {
  69                 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  70                 printf("NOR vBank%d\n", reg);
  71         }
  72 #elif defined(CONFIG_T1023RDB)
  73 #ifdef CONFIG_NAND
  74         puts("NAND\n");
  75 #else
  76         printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) &
  77                GPIO1_VBANK4) >> 15 ? 4 : 0);
  78 #endif
  79 #endif
  80
  81         puts("SERDES Reference Clocks:\n");
  82         if (srds_s1 == 0x95)
  83                 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
  84         else
  85                 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
  86
  87         return 0;
  88 }
  89
  90 #ifdef CONFIG_T1024RDB
  91 static void board_mux_lane(void)
  92 {
  93         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  94         u32 srds_prtcl_s1;
  95         u8 reg = CPLD_READ(misc_ctl_status);
  96
  97         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  98                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  99         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 100
 101         if (srds_prtcl_s1 == 0x95) {
 102                 /* Route Lane B to PCIE */
 103                 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
 104         } else {
 105                 /* Route Lane B to SGMII */
 106                 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
 107         }
 108         CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
 109 }
 110 #endif
 111
 112 int board_early_init_f(void)
 113 {
 114 #if defined(CONFIG_DEEP_SLEEP)
 115         if (is_warm_boot())
 116                 fsl_dp_disable_console();
 117 #endif
 118
 119         return 0;
 120 }
 121
 122 int board_early_init_r(void)
 123 {
 124 #ifdef CONFIG_SYS_FLASH_BASE
 125         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 126         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 127         /*
 128          * Remap Boot flash region to caching-inhibited
 129          * so that flash can be erased properly.
 130          */
 131
 132         /* Flush d-cache and invalidate i-cache of any FLASH data */
 133         flush_dcache();
 134         invalidate_icache();
 135         if (flash_esel == -1) {
 136                 /* very unlikely unless something is messed up */
 137                 puts("Error: Could not find TLB for FLASH BASE\n");
 138                 flash_esel = 2; /* give our best effort to continue */
 139         } else {
 140                 /* invalidate existing TLB entry for flash + promjet */
 141                 disable_tlb(flash_esel);
 142         }
 143
 144         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 145                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 146                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 147 #endif
 148
 149         set_liodns();
 150 #ifdef CONFIG_SYS_DPAA_QBMAN
 151         setup_portals();
 152 #endif
 153 #ifdef CONFIG_T1024RDB
 154         board_mux_lane();
 155 #endif
 156
 157         return 0;
 158 }
 159
 160 unsigned long get_board_sys_clk(void)
 161 {
 162         return CONFIG_SYS_CLK_FREQ;
 163 }
 164
 165 unsigned long get_board_ddr_clk(void)
 166 {
 167         return CONFIG_DDR_CLK_FREQ;
 168 }
 169
 170 int misc_init_r(void)
 171 {
 172         return 0;
 173 }
 174
 175 int ft_board_setup(void *blob, bd_t *bd)
 176 {
 177         phys_addr_t base;
 178         phys_size_t size;
 179
 180         ft_cpu_setup(blob, bd);
 181
 182         base = getenv_bootm_low();
 183         size = getenv_bootm_size();
 184
 185         fdt_fixup_memory(blob, (u64)base, (u64)size);
 186
 187 #ifdef CONFIG_PCI
 188         pci_of_setup(blob, bd);
 189 #endif
 190
 191         fdt_fixup_liodn(blob);
 192         fdt_fixup_dr_usb(blob, bd);
 193
 194 #ifdef CONFIG_SYS_DPAA_FMAN
 195         fdt_fixup_fman_ethernet(blob);
 196         fdt_fixup_board_enet(blob);
 197 #endif
 198
 199         return 0;
 200 }
 201
 202
 203 #ifdef CONFIG_T1023RDB
 204 static u32 t1023rdb_gpio_ctrl(u32 ctrl_type)
 205 {
 206         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 207         u32 gpioval;
 208
 209         setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT);
 210         gpioval = in_be32(&pgpio->gpdat);
 211
 212         switch (ctrl_type) {
 213         case GPIO1_SD_SEL:
 214                 gpioval |= GPIO1_SD_SEL;
 215                 break;
 216         case GPIO1_EMMC_SEL:
 217                 gpioval &= ~GPIO1_SD_SEL;
 218                 break;
 219         case GPIO1_VBANK0:
 220                 gpioval &= ~GPIO1_VBANK_MASK;
 221                 break;
 222         case GPIO1_VBANK4:
 223                 gpioval &= ~GPIO1_VBANK_MASK;
 224                 gpioval |= GPIO1_VBANK4;
 225                 break;
 226         case GPIO1_GET_VAL:
 227                 return gpioval;
 228         default:
 229                 break;
 230         }
 231         out_be32(&pgpio->gpdat, gpioval);
 232
 233         return 0;
 234 }
 235
 236 static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 237                     char * const argv[])
 238 {
 239         if (argc < 2)
 240                 return CMD_RET_USAGE;
 241         if (!strcmp(argv[1], "vbank0"))
 242                 t1023rdb_gpio_ctrl(GPIO1_VBANK0);
 243         else if (!strcmp(argv[1], "vbank4"))
 244                 t1023rdb_gpio_ctrl(GPIO1_VBANK4);
 245         else if (!strcmp(argv[1], "sd"))
 246                 t1023rdb_gpio_ctrl(GPIO1_SD_SEL);
 247         else if (!strcmp(argv[1], "EMMC"))
 248                 t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL);
 249         else
 250                 return CMD_RET_USAGE;
 251         return 0;
 252 }
 253
 254 U_BOOT_CMD(
 255         gpio, 2, 0, gpio_cmd,
 256         "for vbank0/vbank4/SD/eMMC switch control in runtime",
 257         "command (e.g. gpio vbank4)"
 258 );
 259 #endif