2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
13 #include <asm/fsl_law.h>
14 #include <asm/mpc85xx_gpio.h>
17 DECLARE_GLOBAL_DATA_PTR
;
19 void fsl_ddr_board_options(memctl_options_t
*popts
,
21 unsigned int ctrl_num
)
23 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
27 printf("Not supported controller number %d\n", ctrl_num
);
35 /* Get clk_adjust according to the board ddr
36 * freqency and n_banks specified in board_specific_parameters table.
38 ddr_freq
= get_ddr_freq(0) / 1000000;
39 while (pbsp
->datarate_mhz_high
) {
40 if (pbsp
->n_ranks
== pdimm
->n_ranks
&&
41 (pdimm
->rank_density
>> 30) >= pbsp
->rank_gb
) {
42 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
43 popts
->clk_adjust
= pbsp
->clk_adjust
;
44 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
45 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
46 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
55 printf("Error: board specific timing not found\n");
56 printf("for data rate %lu MT/s\n", ddr_freq
);
57 printf("Trying to use the highest speed (%u) parameters\n",
58 pbsp_highest
->datarate_mhz_high
);
59 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
60 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
61 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
62 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
64 panic("DIMM is not supported by this board");
67 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
68 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
69 "wrlvl_ctrl_3 0x%x\n",
70 pbsp
->n_ranks
, pbsp
->datarate_mhz_high
, pbsp
->rank_gb
,
71 pbsp
->clk_adjust
, pbsp
->wrlvl_start
, pbsp
->wrlvl_ctl_2
,
75 * Factors to consider for half-strength driver enable:
76 * - number of DIMMs installed
78 #ifdef CONFIG_SYS_FSL_DDR4
79 popts
->half_strength_driver_enable
= 1;
80 /* optimize cpo for erratum A-009942 */
81 popts
->cpo_sample
= 0x59;
83 popts
->half_strength_driver_enable
= 0;
86 * Write leveling override
88 popts
->wrlvl_override
= 1;
89 popts
->wrlvl_sample
= 0xf;
92 * rtt and rtt_wr override
94 popts
->rtt_override
= 0;
96 /* Enable ZQ calibration */
99 /* DHC_EN =1, ODT = 75 Ohm */
100 #ifdef CONFIG_SYS_FSL_DDR4
101 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_120OHM
);
102 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_120OHM
) |
103 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
105 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_75ohm
);
106 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_75ohm
);
110 #if defined(CONFIG_DEEP_SLEEP)
111 void board_mem_sleep_setup(void)
113 void __iomem
*cpld_base
= (void *)CONFIG_SYS_CPLD_BASE
;
115 /* does not provide HW signals for power management */
116 clrbits_8(cpld_base
+ 0x17, 0x40);
117 /* Disable MCKE isolation */
118 gpio_set_value(2, 0);
125 phys_size_t dram_size
;
127 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
128 puts("Initializing....using SPD\n");
129 dram_size
= fsl_ddr_sdram();
131 dram_size
= fsl_ddr_sdram_size();
133 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
134 dram_size
*= 0x100000;
136 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
140 gd
->ram_size
= dram_size
;