board/freescale/t104xrdb/spl.c

   1 /* Copyright 2013 Freescale Semiconductor, Inc.
   2  *
   3  * SPDX-License-Identifier:    GPL-2.0+
   4  */
   5
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <ns16550.h>
   9 #include <nand.h>
  10 #include <i2c.h>
  11 #include <mmc.h>
  12 #include <fsl_esdhc.h>
  13 #include <spi_flash.h>
  14 #include <asm/mpc85xx_gpio.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 phys_size_t get_effective_memsize(void)
  19 {
  20         return CONFIG_SYS_L3_SIZE;
  21 }
  22
  23 unsigned long get_board_sys_clk(void)
  24 {
  25         return CONFIG_SYS_CLK_FREQ;
  26 }
  27
  28 unsigned long get_board_ddr_clk(void)
  29 {
  30         return CONFIG_DDR_CLK_FREQ;
  31 }
  32
  33 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK        0xFF800000
  34 void board_init_f(ulong bootflag)
  35 {
  36         u32 plat_ratio, sys_clk, uart_clk;
  37 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
  38         u32 porsr1, pinctl;
  39         u32 svr = get_svr();
  40 #endif
  41         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  42
  43 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
  44         if (IS_SVR_REV(svr, 1, 0)) {
  45                 /*
  46                  * There is T1040 SoC issue where NOR, FPGA are inaccessible
  47                  * during NAND boot because IFC signals > IFC_AD7 are not
  48                  * enabled. This workaround changes RCW source to make all
  49                  * signals enabled.
  50                  */
  51                 porsr1 = in_be32(&gur->porsr1);
  52                 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
  53                           | 0x24800000);
  54                 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
  55                          pinctl);
  56         }
  57 #endif
  58
  59         /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
  60         memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
  61
  62         /* Update GD pointer */
  63         gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
  64
  65 #ifdef CONFIG_DEEP_SLEEP
  66         /* disable the console if boot from deep sleep */
  67         if (in_be32(&gur->scrtsr[0]) & (1 << 3))
  68                 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
  69 #endif
  70         /* compiler optimization barrier needed for GCC >= 3.4 */
  71         __asm__ __volatile__("" : : : "memory");
  72
  73         console_init_f();
  74
  75         /* initialize selected port with appropriate baud rate */
  76         sys_clk = get_board_sys_clk();
  77         plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  78         uart_clk = sys_clk * plat_ratio / 2;
  79
  80         NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  81                      uart_clk / 16 / CONFIG_BAUDRATE);
  82
  83         relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
  84 }
  85
  86 void board_init_r(gd_t *gd, ulong dest_addr)
  87 {
  88         bd_t *bd;
  89
  90         bd = (bd_t *)(gd + sizeof(gd_t));
  91         memset(bd, 0, sizeof(bd_t));
  92         gd->bd = bd;
  93         bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
  94         bd->bi_memsize = CONFIG_SYS_L3_SIZE;
  95
  96         probecpu();
  97         get_clocks();
  98         mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  99                         CONFIG_SPL_RELOC_MALLOC_SIZE);
 100
 101 #ifdef CONFIG_SPL_MMC_BOOT
 102         mmc_initialize(bd);
 103 #endif
 104
 105         /* relocate environment function pointers etc. */
 106 #ifdef CONFIG_SPL_NAND_BOOT
 107         nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 108                             (uchar *)CONFIG_ENV_ADDR);
 109 #endif
 110 #ifdef CONFIG_SPL_MMC_BOOT
 111         mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 112                            (uchar *)CONFIG_ENV_ADDR);
 113 #endif
 114 #ifdef CONFIG_SPL_SPI_BOOT
 115         spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 116                            (uchar *)CONFIG_ENV_ADDR);
 117 #endif
 118         gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
 119         gd->env_valid = 1;
 120
 121         i2c_init_all();
 122
 123         puts("\n\n");
 124
 125         gd->ram_size = initdram(0);
 126
 127 #ifdef CONFIG_SPL_MMC_BOOT
 128         mmc_boot();
 129 #elif defined(CONFIG_SPL_SPI_BOOT)
 130         spi_boot();
 131 #elif defined(CONFIG_SPL_NAND_BOOT)
 132         nand_boot();
 133 #endif
 134 }
 135
 136 #ifdef CONFIG_DEEP_SLEEP
 137 void board_mem_sleep_setup(void)
 138 {
 139         void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
 140
 141         /* does not provide HW signals for power management */
 142         clrbits_8(cpld_base + 0x17, 0x40);
 143         /* Disable MCKE isolation */
 144         gpio_set_value(2, 0);
 145         udelay(1);
 146 }
 147 #endif