board/freescale/t104xrdb/tlb.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/mmu.h>
   9
  10 struct fsl_e_tlb_entry tlb_table[] = {
  11         /* TLB 0 - for temp stack in cache */
  12         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  13                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  14                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  15                       0, 0, BOOKE_PAGESZ_4K, 0),
  16         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  17                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  18                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19                       0, 0, BOOKE_PAGESZ_4K, 0),
  20         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  21                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  22                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23                       0, 0, BOOKE_PAGESZ_4K, 0),
  24         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  25                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  26                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  27                       0, 0, BOOKE_PAGESZ_4K, 0),
  28
  29         /* TLB 1 */
  30         /* *I*** - Covers boot page */
  31 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
  32         !defined(CONFIG_SECURE_BOOT)
  33         /*
  34          * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
  35          * SRAM is at 0xfffc0000, it covered the 0xfffff000.
  36          */
  37         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  38                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  39                       0, 0, BOOKE_PAGESZ_256K, 1),
  40
  41 #elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
  42         /*
  43          * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
  44          * the physical address of the SRAM is at 0xbffc0000,
  45          * and virtual address is 0xfffc0000
  46          */
  47
  48         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
  49                       CONFIG_SYS_INIT_L3_ADDR,
  50                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  51                       0, 0, BOOKE_PAGESZ_256K, 1),
  52 #else
  53         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  54                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  55                       0, 0, BOOKE_PAGESZ_4K, 1),
  56 #endif
  57
  58         /* *I*G* - CCSRBAR */
  59         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  60                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  61                       0, 1, BOOKE_PAGESZ_16M, 1),
  62
  63         /* *I*G* - Flash, localbus */
  64         /* This will be changed to *I*G* after relocation to RAM. */
  65         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  66                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  67                       0, 2, BOOKE_PAGESZ_256M, 1),
  68
  69 #ifndef CONFIG_SPL_BUILD
  70         /* *I*G* - PCI */
  71         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  72                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  73                       0, 3, BOOKE_PAGESZ_1G, 1),
  74
  75         /* *I*G* - PCI I/O */
  76         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  77                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  78                       0, 4, BOOKE_PAGESZ_256K, 1),
  79
  80         /* Bman/Qman */
  81 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  82         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  83                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  84                       0, 5, BOOKE_PAGESZ_16M, 1),
  85         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  86                       CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  87                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  88                       0, 6, BOOKE_PAGESZ_16M, 1),
  89 #endif
  90 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  91         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  92                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  93                       0, 7, BOOKE_PAGESZ_16M, 1),
  94         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  95                       CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  96                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  97                       0, 8, BOOKE_PAGESZ_16M, 1),
  98 #endif
  99 #endif
 100 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 101         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 102                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 103                       0, 9, BOOKE_PAGESZ_4M, 1),
 104 #endif
 105 #ifdef CONFIG_SYS_NAND_BASE
 106         /*
 107          * *I*G - NAND
 108          * entry 14 and 15 has been used hard coded, they will be disabled
 109          * in cpu_init_f, so we use entry 16 for nand.
 110          */
 111         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 112                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 113                       0, 10, BOOKE_PAGESZ_64K, 1),
 114 #endif
 115 #ifdef CONFIG_SYS_CPLD_BASE
 116         SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 117                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 118                       0, 11, BOOKE_PAGESZ_256K, 1),
 119 #endif
 120
 121 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 122         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 123                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 124                       0, 12, BOOKE_PAGESZ_1G, 1),
 125         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 126                       CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 127                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 128                       0, 13, BOOKE_PAGESZ_1G, 1)
 129 #endif
 130 };
 131
 132 int num_tlb_entries = ARRAY_SIZE(tlb_table);