2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
13 #include <asm/fsl_law.h>
16 DECLARE_GLOBAL_DATA_PTR
;
18 void fsl_ddr_board_options(memctl_options_t
*popts
,
20 unsigned int ctrl_num
)
22 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
26 printf("Not supported controller number %d\n", ctrl_num
);
33 * we use identical timing for all slots. If needed, change the code
34 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
36 if (popts
->registered_dimm_en
)
42 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
43 * freqency and n_banks specified in board_specific_parameters table.
45 ddr_freq
= get_ddr_freq(0) / 1000000;
46 while (pbsp
->datarate_mhz_high
) {
47 if (pbsp
->n_ranks
== pdimm
->n_ranks
&&
48 (pdimm
->rank_density
>> 30) >= pbsp
->rank_gb
) {
49 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
50 popts
->cpo_override
= pbsp
->cpo
;
51 popts
->write_data_delay
=
52 pbsp
->write_data_delay
;
53 popts
->clk_adjust
= pbsp
->clk_adjust
;
54 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
55 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
56 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
57 popts
->twot_en
= pbsp
->force_2t
;
66 printf("Error: board specific timing not found "
67 "for data rate %lu MT/s\n"
68 "Trying to use the highest speed (%u) parameters\n",
69 ddr_freq
, pbsp_highest
->datarate_mhz_high
);
70 popts
->cpo_override
= pbsp_highest
->cpo
;
71 popts
->write_data_delay
= pbsp_highest
->write_data_delay
;
72 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
73 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
74 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
75 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
76 popts
->twot_en
= pbsp_highest
->force_2t
;
78 panic("DIMM is not supported by this board");
81 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
82 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
83 "wrlvl_ctrl_3 0x%x\n",
84 pbsp
->n_ranks
, pbsp
->datarate_mhz_high
, pbsp
->rank_gb
,
85 pbsp
->clk_adjust
, pbsp
->wrlvl_start
, pbsp
->wrlvl_ctl_2
,
89 * Factors to consider for half-strength driver enable:
90 * - number of DIMMs installed
92 popts
->half_strength_driver_enable
= 0;
94 * Write leveling override
96 popts
->wrlvl_override
= 1;
97 popts
->wrlvl_sample
= 0xf;
100 * Rtt and Rtt_WR override
102 popts
->rtt_override
= 0;
104 /* Enable ZQ calibration */
107 /* DHC_EN =1, ODT = 75 Ohm */
108 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_75ohm
);
109 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_75ohm
);
112 phys_size_t
initdram(int board_type
)
114 phys_size_t dram_size
;
116 puts("Initializing....using SPD\n");
118 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
119 dram_size
= fsl_ddr_sdram();
121 /* DDR has been initialised by first stage boot loader */
122 dram_size
= fsl_ddr_sdram_size();
124 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
125 dram_size
*= 0x100000;