2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
16 #include <fsl_esdhc.h>
21 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
23 DECLARE_GLOBAL_DATA_PTR
;
25 phys_size_t
get_effective_memsize(void)
27 return CONFIG_SYS_L3_SIZE
;
30 unsigned long get_board_sys_clk(void)
32 return CONFIG_SYS_CLK_FREQ
;
35 unsigned long get_board_ddr_clk(void)
37 return CONFIG_DDR_CLK_FREQ
;
40 void board_init_f(ulong bootflag
)
42 u32 plat_ratio
, sys_clk
, ccb_clk
;
43 ccsr_gur_t
*gur
= (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR
;
45 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
46 memcpy((void *)CONFIG_SPL_GD_ADDR
, (void *)gd
, sizeof(gd_t
));
48 /* Update GD pointer */
49 gd
= (gd_t
*)(CONFIG_SPL_GD_ADDR
);
51 /* compiler optimization barrier needed for GCC >= 3.4 */
52 __asm__
__volatile__("" : : : "memory");
56 /* initialize selected port with appropriate baud rate */
57 sys_clk
= get_board_sys_clk();
58 plat_ratio
= (in_be32(&gur
->rcwsr
[0]) >> 25) & 0x1f;
59 ccb_clk
= sys_clk
* plat_ratio
/ 2;
61 NS16550_init((NS16550_t
)CONFIG_SYS_NS16550_COM1
,
62 ccb_clk
/ 16 / CONFIG_BAUDRATE
);
64 puts("\nSD boot...\n");
66 relocate_code(CONFIG_SPL_RELOC_STACK
, (gd_t
*)CONFIG_SPL_GD_ADDR
, 0x0);
69 void board_init_r(gd_t
*gd
, ulong dest_addr
)
73 bd
= (bd_t
*)(gd
+ sizeof(gd_t
));
74 memset(bd
, 0, sizeof(bd_t
));
76 bd
->bi_memstart
= CONFIG_SYS_INIT_L3_ADDR
;
77 bd
->bi_memsize
= CONFIG_SYS_L3_SIZE
;
81 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR
,
82 CONFIG_SPL_RELOC_MALLOC_SIZE
);
83 gd
->flags
|= GD_FLG_FULL_MALLOC_INIT
;
86 mmc_spl_load_image(CONFIG_ENV_OFFSET
, CONFIG_ENV_SIZE
,
87 (uchar
*)CONFIG_ENV_ADDR
);
89 gd
->env_addr
= (ulong
)(CONFIG_ENV_ADDR
);