board/g2000/g2000.c

   1 /*
   2  * (C) Copyright 2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <command.h>
  27
  28 #define MEM_MCOPT1_INIT_VAL     0x00800000
  29 #define MEM_RTR_INIT_VAL        0x04070000
  30 #define MEM_PMIT_INIT_VAL       0x07c00000
  31 #define MEM_MB0CF_INIT_VAL      0x00082001
  32 #define MEM_MB1CF_INIT_VAL      0x04082000
  33 #define MEM_SDTR1_INIT_VAL      0x00854005
  34 #define SDRAM0_CFG_ENABLE       0x80000000
  35
  36 #define CONFIG_SYS_SDRAM_SIZE          0x04000000      /* 64 MB */
  37
  38 int board_early_init_f (void)
  39 {
  40 #if 0 /* test-only */
  41         mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
  42         mtdcr (uicer, 0x00000000);      /* disable all ints */
  43         mtdcr (uiccr, 0x00000010);
  44         mtdcr (uicpr, 0xFFFF7FF0);      /* set int polarities */
  45         mtdcr (uictr, 0x00000010);      /* set int trigger levels */
  46         mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
  47 #else
  48         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  49         mtdcr(uicer, 0x00000000);       /* disable all ints */
  50         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
  51         mtdcr(uicpr, 0xFFFFFFF0);       /* set int polarities */
  52         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
  53         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  54         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  55 #endif
  56
  57 #if 1 /* test-only */
  58         /*
  59          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
  60          */
  61         mtebc (epcr, 0xa8400000); /* ebc always driven */
  62 #endif
  63
  64         return 0;
  65 }
  66
  67
  68 int misc_init_f (void)
  69 {
  70         return 0;  /* dummy implementation */
  71 }
  72
  73
  74 int misc_init_r (void)
  75 {
  76 #if defined(CONFIG_CMD_NAND)
  77         /*
  78          * Set NAND-FLASH GPIO signals to default
  79          */
  80         out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
  81         out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);
  82 #endif
  83
  84         return (0);
  85 }
  86
  87
  88 /*
  89  * Check Board Identity:
  90  */
  91 int checkboard (void)
  92 {
  93         char str[64];
  94         int i = getenv_r ("serial#", str, sizeof(str));
  95
  96         puts ("Board: ");
  97
  98         if (i == -1) {
  99                 puts ("### No HW ID - assuming G2000");
 100         } else {
 101                 puts(str);
 102         }
 103
 104         putc ('\n');
 105
 106         return 0;
 107 }
 108
 109
 110 /* -------------------------------------------------------------------------
 111   G2000 rev B is an embeded design. we don't read for spd of this version.
 112   Doing static SDRAM controller configuration in the following section.
 113    ------------------------------------------------------------------------- */
 114
 115 long int init_sdram_static_settings(void)
 116 {
 117 #define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
 118         /* disable memcontroller so updates work */
 119         mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL );
 120         mtsdram0( mem_rtr   , MEM_RTR_INIT_VAL   );
 121         mtsdram0( mem_pmit  , MEM_PMIT_INIT_VAL  );
 122         mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL );
 123         mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL );
 124         mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL );
 125
 126         /* SDRAM have a power on delay,  500 micro should do */
 127         udelay(500);
 128         mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
 129
 130         return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
 131  }
 132
 133
 134 phys_size_t initdram (int board_type)
 135 {
 136         long int ret;
 137
 138 /* flzt, we can still turn this on in the future */
 139 /* #ifdef CONFIG_SPD_EEPROM
 140         ret = spd_sdram ();
 141 #else
 142         ret = init_sdram_static_settings();
 143 #endif
 144 */
 145
 146         ret = init_sdram_static_settings();
 147
 148         return ret;
 149 }
 150
 151 #if 0 /* test-only !!! */
 152 int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 153 {
 154         ulong ap, cr;
 155
 156         printf("\nEBC registers for PPC405GP:\n");
 157         mfebc(pb0ap, ap); mfebc(pb0cr, cr);
 158         printf("0: AP=%08lx CP=%08lx\n", ap, cr);
 159         mfebc(pb1ap, ap); mfebc(pb1cr, cr);
 160         printf("1: AP=%08lx CP=%08lx\n", ap, cr);
 161         mfebc(pb2ap, ap); mfebc(pb2cr, cr);
 162         printf("2: AP=%08lx CP=%08lx\n", ap, cr);
 163         mfebc(pb3ap, ap); mfebc(pb3cr, cr);
 164         printf("3: AP=%08lx CP=%08lx\n", ap, cr);
 165         mfebc(pb4ap, ap); mfebc(pb4cr, cr);
 166         printf("4: AP=%08lx CP=%08lx\n", ap, cr);
 167         printf("\n");
 168
 169         return 0;
 170 }
 171 U_BOOT_CMD(
 172         dumpebc,        1,      1,      do_dumpebc,
 173         "Dump all EBC registers",
 174         ""
 175 );
 176
 177
 178 int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 179 {
 180         int i;
 181
 182         printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
 183         for (i=0; i<=0x1e0; i++) {
 184                 if (!(i % 0x8)) {
 185                         printf("\n%04x ", i);
 186                 }
 187                 printf("%08lx ", get_dcr(i));
 188         }
 189         printf("\n");
 190
 191         return 0;
 192 }
 193 U_BOOT_CMD(
 194         dumpdcr,        1,      1,      do_dumpdcr,
 195         "Dump all DCR registers",
 196         ""
 197 );
 198
 199
 200 int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 201 {
 202         printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
 203         printf("\n%04x %08x ", 947, mfspr(947));
 204         printf("\n%04x %08x ", 9, mfspr(9));
 205         printf("\n%04x %08x ", 1014, mfspr(1014));
 206         printf("\n%04x %08x ", 1015, mfspr(1015));
 207         printf("\n%04x %08x ", 1010, mfspr(1010));
 208         printf("\n%04x %08x ", 957, mfspr(957));
 209         printf("\n%04x %08x ", 1008, mfspr(1008));
 210         printf("\n%04x %08x ", 1018, mfspr(1018));
 211         printf("\n%04x %08x ", 954, mfspr(954));
 212         printf("\n%04x %08x ", 950, mfspr(950));
 213         printf("\n%04x %08x ", 951, mfspr(951));
 214         printf("\n%04x %08x ", 981, mfspr(981));
 215         printf("\n%04x %08x ", 980, mfspr(980));
 216         printf("\n%04x %08x ", 982, mfspr(982));
 217         printf("\n%04x %08x ", 1012, mfspr(1012));
 218         printf("\n%04x %08x ", 1013, mfspr(1013));
 219         printf("\n%04x %08x ", 948, mfspr(948));
 220         printf("\n%04x %08x ", 949, mfspr(949));
 221         printf("\n%04x %08x ", 1019, mfspr(1019));
 222         printf("\n%04x %08x ", 979, mfspr(979));
 223         printf("\n%04x %08x ", 8, mfspr(8));
 224         printf("\n%04x %08x ", 945, mfspr(945));
 225         printf("\n%04x %08x ", 987, mfspr(987));
 226         printf("\n%04x %08x ", 287, mfspr(287));
 227         printf("\n%04x %08x ", 953, mfspr(953));
 228         printf("\n%04x %08x ", 955, mfspr(955));
 229         printf("\n%04x %08x ", 272, mfspr(272));
 230         printf("\n%04x %08x ", 273, mfspr(273));
 231         printf("\n%04x %08x ", 274, mfspr(274));
 232         printf("\n%04x %08x ", 275, mfspr(275));
 233         printf("\n%04x %08x ", 260, mfspr(260));
 234         printf("\n%04x %08x ", 276, mfspr(276));
 235         printf("\n%04x %08x ", 261, mfspr(261));
 236         printf("\n%04x %08x ", 277, mfspr(277));
 237         printf("\n%04x %08x ", 262, mfspr(262));
 238         printf("\n%04x %08x ", 278, mfspr(278));
 239         printf("\n%04x %08x ", 263, mfspr(263));
 240         printf("\n%04x %08x ", 279, mfspr(279));
 241         printf("\n%04x %08x ", 26, mfspr(26));
 242         printf("\n%04x %08x ", 27, mfspr(27));
 243         printf("\n%04x %08x ", 990, mfspr(990));
 244         printf("\n%04x %08x ", 991, mfspr(991));
 245         printf("\n%04x %08x ", 956, mfspr(956));
 246         printf("\n%04x %08x ", 284, mfspr(284));
 247         printf("\n%04x %08x ", 285, mfspr(285));
 248         printf("\n%04x %08x ", 986, mfspr(986));
 249         printf("\n%04x %08x ", 984, mfspr(984));
 250         printf("\n%04x %08x ", 256, mfspr(256));
 251         printf("\n%04x %08x ", 1, mfspr(1));
 252         printf("\n%04x %08x ", 944, mfspr(944));
 253         printf("\n");
 254
 255         return 0;
 256 }
 257 U_BOOT_CMD(
 258         dumpspr,        1,      1,      do_dumpspr,
 259         "Dump all SPR registers",
 260         ""
 261 );
 262 #endif