2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/mx6-pins.h>
11 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/mxc_i2c.h>
14 #include <fsl_esdhc.h>
16 #include <power/pmic.h>
17 #include <power/ltc3676_pmic.h>
18 #include <power/pfuze100_pmic.h>
22 /* UART1: Function varies per baseboard */
23 static iomux_v3_cfg_t
const uart1_pads
[] = {
24 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
25 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
28 /* UART2: Serial Console */
29 static iomux_v3_cfg_t
const uart2_pads
[] = {
30 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
31 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
34 void setup_iomux_uart(void)
36 SETUP_IOMUX_PADS(uart1_pads
);
37 SETUP_IOMUX_PADS(uart2_pads
);
41 static iomux_v3_cfg_t
const gw5904_emmc_pads
[] = {
42 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
43 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
44 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
45 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
46 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
47 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
48 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
49 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
50 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
51 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
52 IOMUX_PADS(PAD_SD3_RST__SD3_RESET
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
54 /* 4-bit microSD on SD2 */
55 static iomux_v3_cfg_t
const gw5904_mmc_pads
[] = {
56 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
57 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
58 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
59 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
60 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
61 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
63 IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
65 /* 8-bit eMMC on SD2/NAND */
66 static iomux_v3_cfg_t
const gw560x_emmc_sd2_pads
[] = {
67 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
68 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
69 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
70 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
71 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
72 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
73 IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
74 IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
75 IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
76 IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
79 static iomux_v3_cfg_t
const usdhc3_pads
[] = {
80 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
81 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
82 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
83 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
84 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
85 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
86 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
90 static struct i2c_pads_info mx6q_i2c_pad_info0
= {
92 .i2c_mode
= MX6Q_PAD_EIM_D21__I2C1_SCL
| PC
,
93 .gpio_mode
= MX6Q_PAD_EIM_D21__GPIO3_IO21
| PC
,
94 .gp
= IMX_GPIO_NR(3, 21)
97 .i2c_mode
= MX6Q_PAD_EIM_D28__I2C1_SDA
| PC
,
98 .gpio_mode
= MX6Q_PAD_EIM_D28__GPIO3_IO28
| PC
,
99 .gp
= IMX_GPIO_NR(3, 28)
102 static struct i2c_pads_info mx6dl_i2c_pad_info0
= {
104 .i2c_mode
= MX6DL_PAD_EIM_D21__I2C1_SCL
| PC
,
105 .gpio_mode
= MX6DL_PAD_EIM_D21__GPIO3_IO21
| PC
,
106 .gp
= IMX_GPIO_NR(3, 21)
109 .i2c_mode
= MX6DL_PAD_EIM_D28__I2C1_SDA
| PC
,
110 .gpio_mode
= MX6DL_PAD_EIM_D28__GPIO3_IO28
| PC
,
111 .gp
= IMX_GPIO_NR(3, 28)
115 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
116 static struct i2c_pads_info mx6q_i2c_pad_info1
= {
118 .i2c_mode
= MX6Q_PAD_KEY_COL3__I2C2_SCL
| PC
,
119 .gpio_mode
= MX6Q_PAD_KEY_COL3__GPIO4_IO12
| PC
,
120 .gp
= IMX_GPIO_NR(4, 12)
123 .i2c_mode
= MX6Q_PAD_KEY_ROW3__I2C2_SDA
| PC
,
124 .gpio_mode
= MX6Q_PAD_KEY_ROW3__GPIO4_IO13
| PC
,
125 .gp
= IMX_GPIO_NR(4, 13)
128 static struct i2c_pads_info mx6dl_i2c_pad_info1
= {
130 .i2c_mode
= MX6DL_PAD_KEY_COL3__I2C2_SCL
| PC
,
131 .gpio_mode
= MX6DL_PAD_KEY_COL3__GPIO4_IO12
| PC
,
132 .gp
= IMX_GPIO_NR(4, 12)
135 .i2c_mode
= MX6DL_PAD_KEY_ROW3__I2C2_SDA
| PC
,
136 .gpio_mode
= MX6DL_PAD_KEY_ROW3__GPIO4_IO13
| PC
,
137 .gp
= IMX_GPIO_NR(4, 13)
141 /* I2C3: Misc/Expansion */
142 static struct i2c_pads_info mx6q_i2c_pad_info2
= {
144 .i2c_mode
= MX6Q_PAD_GPIO_3__I2C3_SCL
| PC
,
145 .gpio_mode
= MX6Q_PAD_GPIO_3__GPIO1_IO03
| PC
,
146 .gp
= IMX_GPIO_NR(1, 3)
149 .i2c_mode
= MX6Q_PAD_GPIO_6__I2C3_SDA
| PC
,
150 .gpio_mode
= MX6Q_PAD_GPIO_6__GPIO1_IO06
| PC
,
151 .gp
= IMX_GPIO_NR(1, 6)
154 static struct i2c_pads_info mx6dl_i2c_pad_info2
= {
156 .i2c_mode
= MX6DL_PAD_GPIO_3__I2C3_SCL
| PC
,
157 .gpio_mode
= MX6DL_PAD_GPIO_3__GPIO1_IO03
| PC
,
158 .gp
= IMX_GPIO_NR(1, 3)
161 .i2c_mode
= MX6DL_PAD_GPIO_6__I2C3_SDA
| PC
,
162 .gpio_mode
= MX6DL_PAD_GPIO_6__GPIO1_IO06
| PC
,
163 .gp
= IMX_GPIO_NR(1, 6)
167 void setup_ventana_i2c(void)
169 if (is_cpu_type(MXC_CPU_MX6Q
)) {
170 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c_pad_info0
);
171 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c_pad_info1
);
172 setup_i2c(2, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c_pad_info2
);
174 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c_pad_info0
);
175 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c_pad_info1
);
176 setup_i2c(2, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c_pad_info2
);
181 * Baseboard specific GPIO
183 static iomux_v3_cfg_t
const gw51xx_gpio_pads
[] = {
185 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
187 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
189 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| DIO_PAD_CFG
),
191 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(IRQ_PAD_CTRL
)),
194 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| DIO_PAD_CFG
),
196 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20
| DIO_PAD_CFG
),
198 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00
| DIO_PAD_CFG
),
200 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
203 static iomux_v3_cfg_t
const gw52xx_gpio_pads
[] = {
205 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14
| DIO_PAD_CFG
),
207 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11
| DIO_PAD_CFG
),
209 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08
| DIO_PAD_CFG
),
211 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
213 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
215 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| DIO_PAD_CFG
),
217 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(IRQ_PAD_CTRL
)),
219 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
| DIO_PAD_CFG
),
221 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
223 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27
| DIO_PAD_CFG
),
225 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| DIO_PAD_CFG
),
227 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| DIO_PAD_CFG
),
229 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| DIO_PAD_CFG
),
230 /* PCI_RST# (GW522x) */
231 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23
| DIO_PAD_CFG
),
233 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01
| DIO_PAD_CFG
),
235 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
238 static iomux_v3_cfg_t
const gw53xx_gpio_pads
[] = {
240 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14
| DIO_PAD_CFG
),
242 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11
| DIO_PAD_CFG
),
244 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08
| DIO_PAD_CFG
),
246 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| DIO_PAD_CFG
),
248 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
| DIO_PAD_CFG
),
250 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
252 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
254 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
256 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| DIO_PAD_CFG
),
258 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(IRQ_PAD_CTRL
)),
260 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05
| DIO_PAD_CFG
),
262 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27
| DIO_PAD_CFG
),
264 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| DIO_PAD_CFG
),
266 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| DIO_PAD_CFG
),
268 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01
| DIO_PAD_CFG
),
270 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
273 static iomux_v3_cfg_t
const gw54xx_gpio_pads
[] = {
275 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14
| DIO_PAD_CFG
),
277 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11
| DIO_PAD_CFG
),
279 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08
| DIO_PAD_CFG
),
281 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| DIO_PAD_CFG
),
283 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
285 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
287 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
289 IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
| DIO_PAD_CFG
),
291 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21
| DIO_PAD_CFG
),
293 IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24
| DIO_PAD_CFG
),
295 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| DIO_PAD_CFG
),
297 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(IRQ_PAD_CTRL
)),
299 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05
| DIO_PAD_CFG
),
301 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| DIO_PAD_CFG
),
303 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| DIO_PAD_CFG
),
305 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01
| DIO_PAD_CFG
),
307 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17
| DIO_PAD_CFG
),
310 static iomux_v3_cfg_t
const gw551x_gpio_pads
[] = {
312 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
| DIO_PAD_CFG
),
314 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
316 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00
| DIO_PAD_CFG
),
318 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
321 static iomux_v3_cfg_t
const gw552x_gpio_pads
[] = {
323 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08
| DIO_PAD_CFG
),
325 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07
| DIO_PAD_CFG
),
327 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
| DIO_PAD_CFG
),
329 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
331 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
333 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
335 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| DIO_PAD_CFG
),
337 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18
| DIO_PAD_CFG
),
338 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20
| DIO_PAD_CFG
),
339 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21
| DIO_PAD_CFG
),
340 IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22
| DIO_PAD_CFG
),
341 IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23
| DIO_PAD_CFG
),
342 IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25
| DIO_PAD_CFG
),
344 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01
| DIO_PAD_CFG
),
346 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| DIO_PAD_CFG
),
348 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
351 static iomux_v3_cfg_t
const gw553x_gpio_pads
[] = {
353 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14
| DIO_PAD_CFG
),
355 IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10
| DIO_PAD_CFG
),
357 IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11
| DIO_PAD_CFG
),
359 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20
| DIO_PAD_CFG
),
361 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00
| DIO_PAD_CFG
),
363 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
366 static iomux_v3_cfg_t
const gw560x_gpio_pads
[] = {
368 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11
| DIO_PAD_CFG
),
370 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| DIO_PAD_CFG
),
372 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
| DIO_PAD_CFG
),
374 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
376 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
378 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
380 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| DIO_PAD_CFG
),
382 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(IRQ_PAD_CTRL
)),
384 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05
| DIO_PAD_CFG
),
386 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| DIO_PAD_CFG
),
388 IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31
| DIO_PAD_CFG
),
390 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01
| DIO_PAD_CFG
),
392 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
393 /* USBH2_PEN (OTG) */
394 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
396 IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26
| DIO_PAD_CFG
),
399 static iomux_v3_cfg_t
const gw5903_gpio_pads
[] = {
401 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07
| DIO_PAD_CFG
),
403 IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02
| DIO_PAD_CFG
),
405 IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03
| DIO_PAD_CFG
),
407 IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04
| DIO_PAD_CFG
),
408 /* USBH1_PEN (EHCI) */
409 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| DIO_PAD_CFG
),
410 /* USBH2_PEN (OTG) */
411 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
413 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
415 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08
| DIO_PAD_CFG
),
417 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17
| DIO_PAD_CFG
),
419 IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30
| DIO_PAD_CFG
),
421 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14
| DIO_PAD_CFG
),
423 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
425 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25
| DIO_PAD_CFG
),
427 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
429 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08
| DIO_PAD_CFG
),
432 static iomux_v3_cfg_t
const gw5904_gpio_pads
[] = {
434 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
| DIO_PAD_CFG
),
436 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
438 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
440 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
442 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| DIO_PAD_CFG
),
444 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(IRQ_PAD_CTRL
)),
446 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05
| DIO_PAD_CFG
),
448 IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23
| DIO_PAD_CFG
),
450 IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24
| DIO_PAD_CFG
),
452 IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11
| DIO_PAD_CFG
),
454 IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12
| DIO_PAD_CFG
),
456 IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13
| DIO_PAD_CFG
),
458 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00
| DIO_PAD_CFG
),
460 IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15
| DIO_PAD_CFG
),
462 IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14
| DIO_PAD_CFG
),
464 IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13
| DIO_PAD_CFG
),
468 struct dio_cfg gw51xx_dio
[] = {
470 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
476 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
478 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
482 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
484 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
488 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18
) },
490 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT
) },
495 struct dio_cfg gw52xx_dio
[] = {
497 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
503 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
505 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
509 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
511 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
515 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
) },
522 struct dio_cfg gw53xx_dio
[] = {
524 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
530 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
532 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
536 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
538 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
542 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
) },
549 struct dio_cfg gw54xx_dio
[] = {
551 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
) },
553 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT
) },
557 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
559 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
563 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09
) },
565 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT
) },
569 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10
) },
571 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT
) },
576 struct dio_cfg gw551x_dio
[] = {
578 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
580 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
584 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
586 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
591 struct dio_cfg gw552x_dio
[] = {
593 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
599 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
601 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
605 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
607 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
611 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
) },
617 {IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18
) },
623 {IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20
) },
629 {IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21
) },
635 {IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22
) },
641 {IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23
) },
647 {IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25
) },
654 struct dio_cfg gw553x_dio
[] = {
656 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
662 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
664 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
668 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
670 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
674 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18
) },
676 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT
) },
681 struct dio_cfg gw560x_dio
[] = {
683 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
689 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
691 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
695 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
697 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
701 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
) },
708 struct dio_cfg gw5903_dio
[] = {
711 struct dio_cfg gw5904_dio
[] = {
713 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
719 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
721 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
725 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
727 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
731 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
) },
737 {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00
) },
743 {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01
) },
749 {IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02
) },
755 {IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03
) },
761 {IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04
) },
767 {IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05
) },
773 {IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06
) },
779 {IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07
) },
787 * Board Specific GPIO
789 struct ventana gpio_cfg
[GW_UNKNOWN
] = {
792 .gpio_pads
= gw54xx_gpio_pads
,
793 .num_pads
= ARRAY_SIZE(gw54xx_gpio_pads
)/2,
794 .dio_cfg
= gw54xx_dio
,
795 .dio_num
= ARRAY_SIZE(gw54xx_dio
),
801 .pcie_rst
= IMX_GPIO_NR(1, 29),
802 .mezz_pwren
= IMX_GPIO_NR(4, 7),
803 .mezz_irq
= IMX_GPIO_NR(4, 9),
804 .rs485en
= IMX_GPIO_NR(3, 24),
805 .dioi2c_en
= IMX_GPIO_NR(4, 5),
806 .pcie_sson
= IMX_GPIO_NR(1, 20),
807 .otgpwr_en
= IMX_GPIO_NR(3, 22),
808 .mmc_cd
= IMX_GPIO_NR(7, 0),
813 .gpio_pads
= gw51xx_gpio_pads
,
814 .num_pads
= ARRAY_SIZE(gw51xx_gpio_pads
)/2,
815 .dio_cfg
= gw51xx_dio
,
816 .dio_num
= ARRAY_SIZE(gw51xx_dio
),
821 .pcie_rst
= IMX_GPIO_NR(1, 0),
822 .mezz_pwren
= IMX_GPIO_NR(2, 19),
823 .mezz_irq
= IMX_GPIO_NR(2, 18),
824 .gps_shdn
= IMX_GPIO_NR(1, 2),
825 .vidin_en
= IMX_GPIO_NR(5, 20),
826 .wdis
= IMX_GPIO_NR(7, 12),
827 .otgpwr_en
= IMX_GPIO_NR(3, 22),
832 .gpio_pads
= gw52xx_gpio_pads
,
833 .num_pads
= ARRAY_SIZE(gw52xx_gpio_pads
)/2,
834 .dio_cfg
= gw52xx_dio
,
835 .dio_num
= ARRAY_SIZE(gw52xx_dio
),
841 .pcie_rst
= IMX_GPIO_NR(1, 29),
842 .mezz_pwren
= IMX_GPIO_NR(2, 19),
843 .mezz_irq
= IMX_GPIO_NR(2, 18),
844 .gps_shdn
= IMX_GPIO_NR(1, 27),
845 .vidin_en
= IMX_GPIO_NR(3, 31),
846 .usb_sel
= IMX_GPIO_NR(1, 2),
847 .wdis
= IMX_GPIO_NR(7, 12),
848 .msata_en
= GP_MSATA_SEL
,
849 .rs232_en
= GP_RS232_EN
,
850 .otgpwr_en
= IMX_GPIO_NR(3, 22),
851 .vsel_pin
= IMX_GPIO_NR(6, 14),
852 .mmc_cd
= IMX_GPIO_NR(7, 0),
857 .gpio_pads
= gw53xx_gpio_pads
,
858 .num_pads
= ARRAY_SIZE(gw53xx_gpio_pads
)/2,
859 .dio_cfg
= gw53xx_dio
,
860 .dio_num
= ARRAY_SIZE(gw53xx_dio
),
866 .pcie_rst
= IMX_GPIO_NR(1, 29),
867 .mezz_pwren
= IMX_GPIO_NR(2, 19),
868 .mezz_irq
= IMX_GPIO_NR(2, 18),
869 .gps_shdn
= IMX_GPIO_NR(1, 27),
870 .vidin_en
= IMX_GPIO_NR(3, 31),
871 .wdis
= IMX_GPIO_NR(7, 12),
872 .msata_en
= GP_MSATA_SEL
,
873 .rs232_en
= GP_RS232_EN
,
874 .otgpwr_en
= IMX_GPIO_NR(3, 22),
875 .vsel_pin
= IMX_GPIO_NR(6, 14),
876 .mmc_cd
= IMX_GPIO_NR(7, 0),
881 .gpio_pads
= gw54xx_gpio_pads
,
882 .num_pads
= ARRAY_SIZE(gw54xx_gpio_pads
)/2,
883 .dio_cfg
= gw54xx_dio
,
884 .dio_num
= ARRAY_SIZE(gw54xx_dio
),
890 .pcie_rst
= IMX_GPIO_NR(1, 29),
891 .mezz_pwren
= IMX_GPIO_NR(2, 19),
892 .mezz_irq
= IMX_GPIO_NR(2, 18),
893 .rs485en
= IMX_GPIO_NR(7, 1),
894 .vidin_en
= IMX_GPIO_NR(3, 31),
895 .dioi2c_en
= IMX_GPIO_NR(4, 5),
896 .pcie_sson
= IMX_GPIO_NR(1, 20),
897 .wdis
= IMX_GPIO_NR(5, 17),
898 .msata_en
= GP_MSATA_SEL
,
899 .rs232_en
= GP_RS232_EN
,
900 .otgpwr_en
= IMX_GPIO_NR(3, 22),
901 .vsel_pin
= IMX_GPIO_NR(6, 14),
902 .mmc_cd
= IMX_GPIO_NR(7, 0),
907 .gpio_pads
= gw551x_gpio_pads
,
908 .num_pads
= ARRAY_SIZE(gw551x_gpio_pads
)/2,
909 .dio_cfg
= gw551x_dio
,
910 .dio_num
= ARRAY_SIZE(gw551x_dio
),
914 .pcie_rst
= IMX_GPIO_NR(1, 0),
915 .wdis
= IMX_GPIO_NR(7, 12),
920 .gpio_pads
= gw552x_gpio_pads
,
921 .num_pads
= ARRAY_SIZE(gw552x_gpio_pads
)/2,
922 .dio_cfg
= gw552x_dio
,
923 .dio_num
= ARRAY_SIZE(gw552x_dio
),
929 .pcie_rst
= IMX_GPIO_NR(1, 29),
930 .usb_sel
= IMX_GPIO_NR(1, 7),
931 .wdis
= IMX_GPIO_NR(7, 12),
932 .msata_en
= GP_MSATA_SEL
,
937 .gpio_pads
= gw553x_gpio_pads
,
938 .num_pads
= ARRAY_SIZE(gw553x_gpio_pads
)/2,
939 .dio_cfg
= gw553x_dio
,
940 .dio_num
= ARRAY_SIZE(gw553x_dio
),
945 .pcie_rst
= IMX_GPIO_NR(1, 0),
946 .vidin_en
= IMX_GPIO_NR(5, 20),
947 .wdis
= IMX_GPIO_NR(7, 12),
948 .otgpwr_en
= IMX_GPIO_NR(3, 22),
949 .vsel_pin
= IMX_GPIO_NR(6, 14),
950 .mmc_cd
= IMX_GPIO_NR(7, 0),
955 .gpio_pads
= gw560x_gpio_pads
,
956 .num_pads
= ARRAY_SIZE(gw560x_gpio_pads
)/2,
957 .dio_cfg
= gw560x_dio
,
958 .dio_num
= ARRAY_SIZE(gw560x_dio
),
964 .pcie_rst
= IMX_GPIO_NR(4, 31),
965 .mezz_pwren
= IMX_GPIO_NR(2, 19),
966 .mezz_irq
= IMX_GPIO_NR(2, 18),
967 .rs232_en
= GP_RS232_EN
,
968 .vidin_en
= IMX_GPIO_NR(3, 31),
969 .wdis
= IMX_GPIO_NR(7, 12),
970 .otgpwr_en
= IMX_GPIO_NR(4, 15),
971 .mmc_cd
= IMX_GPIO_NR(7, 0),
976 .gpio_pads
= gw5903_gpio_pads
,
977 .num_pads
= ARRAY_SIZE(gw5903_gpio_pads
)/2,
978 .dio_cfg
= gw5903_dio
,
979 .dio_num
= ARRAY_SIZE(gw5903_dio
),
983 .otgpwr_en
= IMX_GPIO_NR(4, 15),
984 .mmc_cd
= IMX_GPIO_NR(6, 11),
989 .gpio_pads
= gw5904_gpio_pads
,
990 .num_pads
= ARRAY_SIZE(gw5904_gpio_pads
)/2,
991 .dio_cfg
= gw5904_dio
,
992 .dio_num
= ARRAY_SIZE(gw5904_dio
),
998 .pcie_rst
= IMX_GPIO_NR(1, 0),
999 .mezz_pwren
= IMX_GPIO_NR(2, 19),
1000 .mezz_irq
= IMX_GPIO_NR(2, 18),
1001 .otgpwr_en
= IMX_GPIO_NR(3, 22),
1005 void setup_iomux_gpio(int board
, struct ventana_board_info
*info
)
1009 if (board
>= GW_UNKNOWN
)
1012 /* board specific iomux */
1013 imx_iomux_v3_setup_multiple_pads(gpio_cfg
[board
].gpio_pads
,
1014 gpio_cfg
[board
].num_pads
);
1017 if (gpio_cfg
[board
].rs232_en
) {
1018 gpio_request(gpio_cfg
[board
].rs232_en
, "rs232_en#");
1019 gpio_direction_output(gpio_cfg
[board
].rs232_en
, 0);
1022 /* GW522x Uses GPIO3_IO23 for PCIE_RST# */
1023 if (board
== GW52xx
&& info
->model
[4] == '2')
1024 gpio_cfg
[board
].pcie_rst
= IMX_GPIO_NR(3, 23);
1026 /* assert PCI_RST# */
1027 gpio_request(gpio_cfg
[board
].pcie_rst
, "pci_rst#");
1028 gpio_direction_output(gpio_cfg
[board
].pcie_rst
, 0);
1030 /* turn off (active-high) user LED's */
1031 for (i
= 0; i
< ARRAY_SIZE(gpio_cfg
[board
].leds
); i
++) {
1033 if (gpio_cfg
[board
].leds
[i
]) {
1034 sprintf(name
, "led_user%d", i
);
1035 gpio_request(gpio_cfg
[board
].leds
[i
], name
);
1036 gpio_direction_output(gpio_cfg
[board
].leds
[i
], 1);
1040 /* MSATA Enable - default to PCI */
1041 if (gpio_cfg
[board
].msata_en
) {
1042 gpio_request(gpio_cfg
[board
].msata_en
, "msata_en");
1043 gpio_direction_output(gpio_cfg
[board
].msata_en
, 0);
1046 /* Expansion Mezzanine IO */
1047 if (gpio_cfg
[board
].mezz_pwren
) {
1048 gpio_request(gpio_cfg
[board
].mezz_pwren
, "mezz_pwr");
1049 gpio_direction_output(gpio_cfg
[board
].mezz_pwren
, 0);
1051 if (gpio_cfg
[board
].mezz_irq
) {
1052 gpio_request(gpio_cfg
[board
].mezz_irq
, "mezz_irq#");
1053 gpio_direction_input(gpio_cfg
[board
].mezz_irq
);
1056 /* RS485 Transmit Enable */
1057 if (gpio_cfg
[board
].rs485en
) {
1058 gpio_request(gpio_cfg
[board
].rs485en
, "rs485_en");
1059 gpio_direction_output(gpio_cfg
[board
].rs485en
, 0);
1063 if (gpio_cfg
[board
].gps_shdn
) {
1064 gpio_request(gpio_cfg
[board
].gps_shdn
, "gps_shdn");
1065 gpio_direction_output(gpio_cfg
[board
].gps_shdn
, 1);
1068 /* Analog video codec power enable */
1069 if (gpio_cfg
[board
].vidin_en
) {
1070 gpio_request(gpio_cfg
[board
].vidin_en
, "anavidin_en");
1071 gpio_direction_output(gpio_cfg
[board
].vidin_en
, 1);
1075 if (gpio_cfg
[board
].dioi2c_en
) {
1076 gpio_request(gpio_cfg
[board
].dioi2c_en
, "dioi2c_dis#");
1077 gpio_direction_output(gpio_cfg
[board
].dioi2c_en
, 0);
1080 /* PCICK_SSON: disable spread-spectrum clock */
1081 if (gpio_cfg
[board
].pcie_sson
) {
1082 gpio_request(gpio_cfg
[board
].pcie_sson
, "pci_sson");
1083 gpio_direction_output(gpio_cfg
[board
].pcie_sson
, 0);
1086 /* USBOTG mux routing */
1087 if (gpio_cfg
[board
].usb_sel
) {
1088 gpio_request(gpio_cfg
[board
].usb_sel
, "usb_pcisel");
1089 gpio_direction_output(gpio_cfg
[board
].usb_sel
, 0);
1092 /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1093 if (gpio_cfg
[board
].wdis
) {
1094 gpio_request(gpio_cfg
[board
].wdis
, "wlan_dis");
1095 gpio_direction_output(gpio_cfg
[board
].wdis
, 1);
1099 if (gpio_cfg
[board
].otgpwr_en
) {
1100 gpio_request(gpio_cfg
[board
].otgpwr_en
, "usbotg_pwr");
1101 gpio_direction_output(gpio_cfg
[board
].otgpwr_en
, 0);
1104 /* sense vselect pin to see if we support uhs-i */
1105 if (gpio_cfg
[board
].vsel_pin
) {
1106 gpio_request(gpio_cfg
[board
].vsel_pin
, "sd3_vselect");
1107 gpio_direction_input(gpio_cfg
[board
].vsel_pin
);
1108 gpio_cfg
[board
].usd_vsel
= !gpio_get_value(gpio_cfg
[board
].vsel_pin
);
1112 if (gpio_cfg
[board
].mmc_cd
) {
1113 gpio_request(gpio_cfg
[board
].mmc_cd
, "sd_cd");
1114 gpio_direction_input(gpio_cfg
[board
].mmc_cd
);
1117 /* Anything else board specific */
1120 gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
1121 gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
1124 gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
1125 gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
1126 gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
1127 gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
1128 gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
1129 gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
1130 gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
1131 gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
1132 gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#");
1133 gpio_direction_input(IMX_GPIO_NR(4, 6));
1134 gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst");
1135 gpio_direction_output(IMX_GPIO_NR(4, 8), 1);
1136 gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
1137 gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
1140 gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
1141 gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
1142 gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
1143 gpio_direction_output(IMX_GPIO_NR(5, 12), 1);
1144 gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#");
1145 gpio_direction_output(IMX_GPIO_NR(5, 13), 1);
1146 gpio_request(IMX_GPIO_NR(1, 15), "m2_off#");
1147 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
1148 gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#");
1149 gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
1150 gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
1151 gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
1156 /* setup GPIO pinmux and default configuration per baseboard and env */
1157 void setup_board_gpio(int board
, struct ventana_board_info
*info
)
1163 int quiet
= simple_strtol(getenv("quiet"), NULL
, 10);
1165 if (board
>= GW_UNKNOWN
)
1169 if (gpio_cfg
[board
].rs232_en
) {
1170 gpio_direction_output(gpio_cfg
[board
].rs232_en
,
1171 (hwconfig("rs232")) ? 0 : 1);
1175 if (gpio_cfg
[board
].msata_en
&& is_cpu_type(MXC_CPU_MX6Q
)) {
1176 gpio_direction_output(GP_MSATA_SEL
,
1177 (hwconfig("msata")) ? 1 : 0);
1180 /* USBOTG Select (PCISKT or FrontPanel) */
1181 if (gpio_cfg
[board
].usb_sel
) {
1182 gpio_direction_output(gpio_cfg
[board
].usb_sel
,
1183 (hwconfig("usb_pcisel")) ? 1 : 0);
1187 * Configure DIO pinmux/padctl registers
1188 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1190 for (i
= 0; i
< gpio_cfg
[board
].dio_num
; i
++) {
1191 struct dio_cfg
*cfg
= &gpio_cfg
[board
].dio_cfg
[i
];
1192 iomux_v3_cfg_t ctrl
= DIO_PAD_CFG
;
1193 unsigned cputype
= is_cpu_type(MXC_CPU_MX6Q
) ? 0 : 1;
1195 if (!cfg
->gpio_padmux
[0] && !cfg
->gpio_padmux
[1])
1197 sprintf(arg
, "dio%d", i
);
1200 s
= hwconfig_subarg(arg
, "padctrl", &len
);
1202 ctrl
= MUX_PAD_CTRL(simple_strtoul(s
, NULL
, 16)
1203 & 0x1ffff) | MUX_MODE_SION
;
1205 if (hwconfig_subarg_cmp(arg
, "mode", "gpio")) {
1207 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i
,
1208 (cfg
->gpio_param
/32)+1,
1212 imx_iomux_v3_setup_pad(cfg
->gpio_padmux
[cputype
] |
1214 gpio_requestf(cfg
->gpio_param
, "dio%d", i
);
1215 gpio_direction_input(cfg
->gpio_param
);
1216 } else if (hwconfig_subarg_cmp(arg
, "mode", "pwm") &&
1218 if (!cfg
->pwm_param
) {
1219 printf("DIO%d: Error: pwm config invalid\n",
1224 printf("DIO%d: pwm%d\n", i
, cfg
->pwm_param
);
1225 imx_iomux_v3_setup_pad(cfg
->pwm_padmux
[cputype
] |
1226 MUX_PAD_CTRL(ctrl
));
1231 if (gpio_cfg
[board
].msata_en
&& is_cpu_type(MXC_CPU_MX6Q
)) {
1232 printf("MSATA: %s\n", (hwconfig("msata") ?
1233 "enabled" : "disabled"));
1235 if (gpio_cfg
[board
].rs232_en
) {
1236 printf("RS232: %s\n", (hwconfig("rs232")) ?
1237 "enabled" : "disabled");
1242 /* setup board specific PMIC */
1243 void setup_pmic(void)
1246 struct ventana_board_info ventana_info
;
1247 int board
= read_eeprom(CONFIG_I2C_GSC
, &ventana_info
);
1248 const int i2c_pmic
= 1;
1251 i2c_set_bus_num(i2c_pmic
);
1253 /* configure PFUZE100 PMIC */
1254 if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR
)) {
1255 debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR
);
1256 power_pfuze100_init(i2c_pmic
);
1257 p
= pmic_get("PFUZE100");
1258 if (p
&& !pmic_probe(p
)) {
1259 pmic_reg_read(p
, PFUZE100_DEVICEID
, ®
);
1260 printf("PMIC: PFUZE100 ID=0x%02x\n", reg
);
1262 /* Set VGEN1 to 1.5V and enable */
1263 pmic_reg_read(p
, PFUZE100_VGEN1VOL
, ®
);
1264 reg
&= ~(LDO_VOL_MASK
);
1265 reg
|= (LDOA_1_50V
| LDO_EN
);
1266 pmic_reg_write(p
, PFUZE100_VGEN1VOL
, reg
);
1268 /* Set SWBST to 5.0V and enable */
1269 pmic_reg_read(p
, PFUZE100_SWBSTCON1
, ®
);
1270 reg
&= ~(SWBST_MODE_MASK
| SWBST_VOL_MASK
);
1271 reg
|= (SWBST_5_00V
| (SWBST_MODE_AUTO
<< SWBST_MODE_SHIFT
));
1272 pmic_reg_write(p
, PFUZE100_SWBSTCON1
, reg
);
1276 /* configure LTC3676 PMIC */
1277 else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR
)) {
1278 debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR
);
1279 power_ltc3676_init(i2c_pmic
);
1280 p
= pmic_get("LTC3676_PMIC");
1281 if (!p
|| pmic_probe(p
))
1283 puts("PMIC: LTC3676\n");
1285 * set board-specific scalar for max CPU frequency
1286 * per CPU based on the LDO enabled Operating Ranges
1287 * defined in the respective IMX6DQ and IMX6SDL
1288 * datasheets. The voltage resulting from the R1/R2
1289 * feedback inputs on Ventana is 1308mV. Note that this
1290 * is a bit shy of the Vmin of 1350mV in the datasheet
1291 * for LDO enabled mode but is as high as we can go.
1295 /* mask PGOOD during SW3 transition */
1296 pmic_reg_write(p
, LTC3676_DVB3B
,
1297 0x1f | LTC3676_PGOOD_MASK
);
1298 /* set SW3 (VDD_ARM) */
1299 pmic_reg_write(p
, LTC3676_DVB3A
, 0x1f);
1302 /* mask PGOOD during SW1 transition */
1303 pmic_reg_write(p
, LTC3676_DVB3B
,
1304 0x1f | LTC3676_PGOOD_MASK
);
1305 /* set SW3 (VDD_ARM) */
1306 pmic_reg_write(p
, LTC3676_DVB3A
, 0x1f);
1308 /* mask PGOOD during SW4 transition */
1309 pmic_reg_write(p
, LTC3676_DVB4B
,
1310 0x1f | LTC3676_PGOOD_MASK
);
1311 /* set SW4 (VDD_SOC) */
1312 pmic_reg_write(p
, LTC3676_DVB4A
, 0x1f);
1315 /* mask PGOOD during SW1 transition */
1316 pmic_reg_write(p
, LTC3676_DVB1B
,
1317 0x1f | LTC3676_PGOOD_MASK
);
1318 /* set SW1 (VDD_SOC) */
1319 pmic_reg_write(p
, LTC3676_DVB1A
, 0x1f);
1321 /* mask PGOOD during SW3 transition */
1322 pmic_reg_write(p
, LTC3676_DVB3B
,
1323 0x1f | LTC3676_PGOOD_MASK
);
1324 /* set SW3 (VDD_ARM) */
1325 pmic_reg_write(p
, LTC3676_DVB3A
, 0x1f);
1330 #ifdef CONFIG_FSL_ESDHC
1331 static struct fsl_esdhc_cfg usdhc_cfg
[2];
1333 int board_mmc_init(bd_t
*bis
)
1335 struct ventana_board_info ventana_info
;
1336 int board_type
= read_eeprom(CONFIG_I2C_GSC
, &ventana_info
);
1339 switch (board_type
) {
1344 /* usdhc3: 4bit microSD */
1345 SETUP_IOMUX_PADS(usdhc3_pads
);
1346 usdhc_cfg
[0].esdhc_base
= USDHC3_BASE_ADDR
;
1347 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
1348 usdhc_cfg
[0].max_bus_width
= 4;
1349 return fsl_esdhc_initialize(bis
, &usdhc_cfg
[0]);
1351 /* usdhc2: 8-bit eMMC */
1352 SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads
);
1353 usdhc_cfg
[0].esdhc_base
= USDHC2_BASE_ADDR
;
1354 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
1355 usdhc_cfg
[0].max_bus_width
= 8;
1356 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[0]);
1359 /* usdhc3: 4-bit microSD */
1360 SETUP_IOMUX_PADS(usdhc3_pads
);
1361 usdhc_cfg
[1].esdhc_base
= USDHC3_BASE_ADDR
;
1362 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
1363 usdhc_cfg
[1].max_bus_width
= 4;
1364 return fsl_esdhc_initialize(bis
, &usdhc_cfg
[1]);
1366 /* usdhc3: 8-bit eMMC */
1367 SETUP_IOMUX_PADS(gw5904_emmc_pads
);
1368 usdhc_cfg
[0].esdhc_base
= USDHC3_BASE_ADDR
;
1369 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
1370 usdhc_cfg
[0].max_bus_width
= 8;
1371 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[0]);
1374 /* usdhc2: 4-bit microSD */
1375 SETUP_IOMUX_PADS(gw5904_mmc_pads
);
1376 usdhc_cfg
[1].esdhc_base
= USDHC2_BASE_ADDR
;
1377 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
1378 usdhc_cfg
[1].max_bus_width
= 4;
1379 return fsl_esdhc_initialize(bis
, &usdhc_cfg
[1]);
1381 /* usdhc3: 8bit eMMC */
1382 SETUP_IOMUX_PADS(gw5904_emmc_pads
);
1383 usdhc_cfg
[0].esdhc_base
= USDHC3_BASE_ADDR
;
1384 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
1385 usdhc_cfg
[0].max_bus_width
= 8;
1386 return fsl_esdhc_initialize(bis
, &usdhc_cfg
[0]);
1388 /* doesn't have MMC */
1393 int board_mmc_getcd(struct mmc
*mmc
)
1395 struct ventana_board_info ventana_info
;
1396 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
1397 int board
= read_eeprom(CONFIG_I2C_GSC
, &ventana_info
);
1398 int gpio
= gpio_cfg
[board
].mmc_cd
;
1403 /* emmc is always present */
1404 if (cfg
->esdhc_base
== USDHC2_BASE_ADDR
)
1409 /* emmc is always present */
1410 if (cfg
->esdhc_base
== USDHC3_BASE_ADDR
)
1416 debug("%s: gpio%d=%d\n", __func__
, gpio
, gpio_get_value(gpio
));
1417 return !gpio_get_value(gpio
);
1423 #endif /* CONFIG_FSL_ESDHC */