]> git.ipfire.org Git - people/ms/u-boot.git/blob - board/gateworks/gw_ventana/gw_ventana.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge git://git.denx.de/u-boot-fsl-qoriq
[people/ms/u-boot.git] / board / gateworks / gw_ventana / gw_ventana.c
1 /*
2 * Copyright (C) 2013 Gateworks Corporation
3 *
4 * Author: Tim Harvey <tharvey@gateworks.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/gpio.h>
17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/imx-common/sata.h>
19 #include <asm/imx-common/spi.h>
20 #include <asm/imx-common/video.h>
21 #include <asm/io.h>
22 #include <dm.h>
23 #include <dm/platform_data/serial_mxc.h>
24 #include <hwconfig.h>
25 #include <i2c.h>
26 #include <fdt_support.h>
27 #include <fsl_esdhc.h>
28 #include <jffs2/load_kernel.h>
29 #include <linux/ctype.h>
30 #include <miiphy.h>
31 #include <mtd_node.h>
32 #include <netdev.h>
33 #include <pci.h>
34 #include <power/pmic.h>
35 #include <power/ltc3676_pmic.h>
36 #include <power/pfuze100_pmic.h>
37 #include <fdt_support.h>
38 #include <jffs2/load_kernel.h>
39 #include <spi_flash.h>
40
41 #include "gsc.h"
42 #include "common.h"
43
44 DECLARE_GLOBAL_DATA_PTR;
45
46
47 /*
48 * EEPROM board info struct populated by read_eeprom so that we only have to
49 * read it once.
50 */
51 struct ventana_board_info ventana_info;
52
53 static int board_type;
54
55 /* ENET */
56 static iomux_v3_cfg_t const enet_pads[] = {
57 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
58 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
59 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
60 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
61 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
62 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
63 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
64 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
65 MUX_PAD_CTRL(ENET_PAD_CTRL)),
66 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
67 MUX_PAD_CTRL(ENET_PAD_CTRL)),
68 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
74 MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 /* PHY nRST */
76 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
77 };
78
79 #ifdef CONFIG_CMD_NAND
80 static iomux_v3_cfg_t const nfc_pads[] = {
81 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
82 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
83 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
84 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
85 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
86 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
87 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
88 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
89 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
90 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
92 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 };
97
98 static void setup_gpmi_nand(void)
99 {
100 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
101
102 /* config gpmi nand iomux */
103 SETUP_IOMUX_PADS(nfc_pads);
104
105 /* config gpmi and bch clock to 100 MHz */
106 clrsetbits_le32(&mxc_ccm->cs2cdr,
107 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
108 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
109 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
110 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
111 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
112 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
113
114 /* enable gpmi and bch clock gating */
115 setbits_le32(&mxc_ccm->CCGR4,
116 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
117 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
118 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
119 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
120 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
121
122 /* enable apbh clock gating */
123 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
124 }
125 #endif
126
127 static void setup_iomux_enet(int gpio)
128 {
129 SETUP_IOMUX_PADS(enet_pads);
130
131 /* toggle PHY_RST# */
132 gpio_request(gpio, "phy_rst#");
133 gpio_direction_output(gpio, 0);
134 mdelay(10);
135 gpio_set_value(gpio, 1);
136 mdelay(100);
137 }
138
139 #ifdef CONFIG_USB_EHCI_MX6
140 static iomux_v3_cfg_t const usb_pads[] = {
141 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
142 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
143 /* OTG PWR */
144 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
145 };
146
147 int board_ehci_hcd_init(int port)
148 {
149 int gpio;
150
151 SETUP_IOMUX_PADS(usb_pads);
152
153 /* Reset USB HUB */
154 switch (board_type) {
155 case GW53xx:
156 case GW552x:
157 gpio = (IMX_GPIO_NR(1, 9));
158 break;
159 case GW54proto:
160 case GW54xx:
161 gpio = (IMX_GPIO_NR(1, 16));
162 break;
163 default:
164 return 0;
165 }
166
167 /* request and toggle hub rst */
168 gpio_request(gpio, "usb_hub_rst#");
169 gpio_direction_output(gpio, 0);
170 mdelay(2);
171 gpio_set_value(gpio, 1);
172
173 return 0;
174 }
175
176 int board_ehci_power(int port, int on)
177 {
178 /* enable OTG VBUS */
179 if (!port && board_type < GW_UNKNOWN) {
180 if (gpio_cfg[board_type].otgpwr_en)
181 gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
182 }
183 return 0;
184 }
185 #endif /* CONFIG_USB_EHCI_MX6 */
186
187 #ifdef CONFIG_MXC_SPI
188 iomux_v3_cfg_t const ecspi1_pads[] = {
189 /* SS1 */
190 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
191 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
192 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
193 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
194 };
195
196 int board_spi_cs_gpio(unsigned bus, unsigned cs)
197 {
198 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
199 }
200
201 static void setup_spi(void)
202 {
203 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
204 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
205 SETUP_IOMUX_PADS(ecspi1_pads);
206 }
207 #endif
208
209 /* configure eth0 PHY board-specific LED behavior */
210 int board_phy_config(struct phy_device *phydev)
211 {
212 unsigned short val;
213
214 /* Marvel 88E1510 */
215 if (phydev->phy_id == 0x1410dd1) {
216 /*
217 * Page 3, Register 16: LED[2:0] Function Control Register
218 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
219 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
220 */
221 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
222 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
223 val &= 0xff00;
224 val |= 0x0017;
225 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
226 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
227 }
228
229 /* TI DP83867 */
230 else if (phydev->phy_id == 0x2000a231) {
231 /* configure register 0x170 for ref CLKOUT */
232 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
233 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
234 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
235 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
236 val &= ~0x1f00;
237 val |= 0x0b00; /* chD tx clock*/
238 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
239 }
240
241 if (phydev->drv->config)
242 phydev->drv->config(phydev);
243
244 return 0;
245 }
246
247 #ifdef CONFIG_MV88E61XX_SWITCH
248 int mv88e61xx_hw_reset(struct phy_device *phydev)
249 {
250 struct mii_dev *bus = phydev->bus;
251
252 /* GPIO[0] output, CLK125 */
253 debug("enabling RGMII_REFCLK\n");
254 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
255 0x1a /*MV_SCRATCH_MISC*/,
256 (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
257 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
258 0x1a /*MV_SCRATCH_MISC*/,
259 (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
260
261 /* RGMII delay - Physical Control register bit[15:14] */
262 debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
263 /* forced 1000mbps full-duplex link */
264 bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
265 phydev->autoneg = AUTONEG_DISABLE;
266 phydev->speed = SPEED_1000;
267 phydev->duplex = DUPLEX_FULL;
268
269 /* LED configuration: 7:4-green (8=Activity) 3:0 amber (9=10Link) */
270 bus->write(bus, 0x10, 0, 0x16, 0x8089);
271 bus->write(bus, 0x11, 0, 0x16, 0x8089);
272 bus->write(bus, 0x12, 0, 0x16, 0x8089);
273 bus->write(bus, 0x13, 0, 0x16, 0x8089);
274
275 return 0;
276 }
277 #endif // CONFIG_MV88E61XX_SWITCH
278
279 int board_eth_init(bd_t *bis)
280 {
281 #ifdef CONFIG_FEC_MXC
282 struct ventana_board_info *info = &ventana_info;
283
284 if (test_bit(EECONFIG_ETH0, info->config)) {
285 setup_iomux_enet(GP_PHY_RST);
286 cpu_eth_init(bis);
287 }
288 #endif
289
290 #ifdef CONFIG_E1000
291 e1000_initialize(bis);
292 #endif
293
294 #ifdef CONFIG_CI_UDC
295 /* For otg ethernet*/
296 usb_eth_initialize(bis);
297 #endif
298
299 /* default to the first detected enet dev */
300 if (!getenv("ethprime")) {
301 struct eth_device *dev = eth_get_dev_by_index(0);
302 if (dev) {
303 setenv("ethprime", dev->name);
304 printf("set ethprime to %s\n", getenv("ethprime"));
305 }
306 }
307
308 return 0;
309 }
310
311 #if defined(CONFIG_VIDEO_IPUV3)
312
313 static void enable_hdmi(struct display_info_t const *dev)
314 {
315 imx_enable_hdmi_phy();
316 }
317
318 static int detect_i2c(struct display_info_t const *dev)
319 {
320 return i2c_set_bus_num(dev->bus) == 0 &&
321 i2c_probe(dev->addr) == 0;
322 }
323
324 static void enable_lvds(struct display_info_t const *dev)
325 {
326 struct iomuxc *iomux = (struct iomuxc *)
327 IOMUXC_BASE_ADDR;
328
329 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
330 u32 reg = readl(&iomux->gpr[2]);
331 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
332 writel(reg, &iomux->gpr[2]);
333
334 /* Enable Backlight */
335 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
336 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
337 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
338 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
339 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
340 }
341
342 struct display_info_t const displays[] = {{
343 /* HDMI Output */
344 .bus = -1,
345 .addr = 0,
346 .pixfmt = IPU_PIX_FMT_RGB24,
347 .detect = detect_hdmi,
348 .enable = enable_hdmi,
349 .mode = {
350 .name = "HDMI",
351 .refresh = 60,
352 .xres = 1024,
353 .yres = 768,
354 .pixclock = 15385,
355 .left_margin = 220,
356 .right_margin = 40,
357 .upper_margin = 21,
358 .lower_margin = 7,
359 .hsync_len = 60,
360 .vsync_len = 10,
361 .sync = FB_SYNC_EXT,
362 .vmode = FB_VMODE_NONINTERLACED
363 } }, {
364 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
365 .bus = 2,
366 .addr = 0x4,
367 .pixfmt = IPU_PIX_FMT_LVDS666,
368 .detect = detect_i2c,
369 .enable = enable_lvds,
370 .mode = {
371 .name = "Hannstar-XGA",
372 .refresh = 60,
373 .xres = 1024,
374 .yres = 768,
375 .pixclock = 15385,
376 .left_margin = 220,
377 .right_margin = 40,
378 .upper_margin = 21,
379 .lower_margin = 7,
380 .hsync_len = 60,
381 .vsync_len = 10,
382 .sync = FB_SYNC_EXT,
383 .vmode = FB_VMODE_NONINTERLACED
384 } }, {
385 /* DLC700JMG-T-4 */
386 .bus = 0,
387 .addr = 0,
388 .detect = NULL,
389 .enable = enable_lvds,
390 .pixfmt = IPU_PIX_FMT_LVDS666,
391 .mode = {
392 .name = "DLC700JMGT4",
393 .refresh = 60,
394 .xres = 1024, /* 1024x600active pixels */
395 .yres = 600,
396 .pixclock = 15385, /* 64MHz */
397 .left_margin = 220,
398 .right_margin = 40,
399 .upper_margin = 21,
400 .lower_margin = 7,
401 .hsync_len = 60,
402 .vsync_len = 10,
403 .sync = FB_SYNC_EXT,
404 .vmode = FB_VMODE_NONINTERLACED
405 } }, {
406 /* DLC800FIG-T-3 */
407 .bus = 0,
408 .addr = 0,
409 .detect = NULL,
410 .enable = enable_lvds,
411 .pixfmt = IPU_PIX_FMT_LVDS666,
412 .mode = {
413 .name = "DLC800FIGT3",
414 .refresh = 60,
415 .xres = 1024, /* 1024x768 active pixels */
416 .yres = 768,
417 .pixclock = 15385, /* 64MHz */
418 .left_margin = 220,
419 .right_margin = 40,
420 .upper_margin = 21,
421 .lower_margin = 7,
422 .hsync_len = 60,
423 .vsync_len = 10,
424 .sync = FB_SYNC_EXT,
425 .vmode = FB_VMODE_NONINTERLACED
426 } } };
427 size_t display_count = ARRAY_SIZE(displays);
428
429 static void setup_display(void)
430 {
431 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
432 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
433 int reg;
434
435 enable_ipu_clock();
436 imx_setup_hdmi();
437 /* Turn on LDB0,IPU,IPU DI0 clocks */
438 reg = __raw_readl(&mxc_ccm->CCGR3);
439 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
440 writel(reg, &mxc_ccm->CCGR3);
441
442 /* set LDB0, LDB1 clk select to 011/011 */
443 reg = readl(&mxc_ccm->cs2cdr);
444 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
445 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
446 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
447 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
448 writel(reg, &mxc_ccm->cs2cdr);
449
450 reg = readl(&mxc_ccm->cscmr2);
451 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
452 writel(reg, &mxc_ccm->cscmr2);
453
454 reg = readl(&mxc_ccm->chsccdr);
455 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
456 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
457 writel(reg, &mxc_ccm->chsccdr);
458
459 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
460 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
461 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
462 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
463 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
464 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
465 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
466 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
467 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
468 writel(reg, &iomux->gpr[2]);
469
470 reg = readl(&iomux->gpr[3]);
471 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
472 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
473 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
474 writel(reg, &iomux->gpr[3]);
475
476 /* LVDS Backlight GPIO on LVDS connector - output low */
477 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
478 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
479 }
480 #endif /* CONFIG_VIDEO_IPUV3 */
481
482 /* setup board specific PMIC */
483 int power_init_board(void)
484 {
485 setup_pmic();
486 return 0;
487 }
488
489 #if defined(CONFIG_CMD_PCI)
490 int imx6_pcie_toggle_reset(void)
491 {
492 if (board_type < GW_UNKNOWN) {
493 uint pin = gpio_cfg[board_type].pcie_rst;
494 gpio_request(pin, "pci_rst#");
495 gpio_direction_output(pin, 0);
496 mdelay(50);
497 gpio_direction_output(pin, 1);
498 }
499 return 0;
500 }
501
502 /*
503 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
504 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
505 * properly and assert reset for 100ms.
506 */
507 #define MAX_PCI_DEVS 32
508 struct pci_dev {
509 pci_dev_t devfn;
510 unsigned short vendor;
511 unsigned short device;
512 unsigned short class;
513 unsigned short busno; /* subbordinate busno */
514 struct pci_dev *ppar;
515 };
516 struct pci_dev pci_devs[MAX_PCI_DEVS];
517 int pci_devno;
518 int pci_bridgeno;
519
520 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
521 unsigned short vendor, unsigned short device,
522 unsigned short class)
523 {
524 int i;
525 u32 dw;
526 struct pci_dev *pdev = &pci_devs[pci_devno++];
527
528 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
529 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
530
531 /* store array of devs for later use in device-tree fixup */
532 pdev->devfn = dev;
533 pdev->vendor = vendor;
534 pdev->device = device;
535 pdev->class = class;
536 pdev->ppar = NULL;
537 if (class == PCI_CLASS_BRIDGE_PCI)
538 pdev->busno = ++pci_bridgeno;
539 else
540 pdev->busno = 0;
541
542 /* fixup RC - it should be 00:00.0 not 00:01.0 */
543 if (PCI_BUS(dev) == 0)
544 pdev->devfn = 0;
545
546 /* find dev's parent */
547 for (i = 0; i < pci_devno; i++) {
548 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
549 pdev->ppar = &pci_devs[i];
550 break;
551 }
552 }
553
554 /* assert downstream PERST# */
555 if (vendor == PCI_VENDOR_ID_PLX &&
556 (device & 0xfff0) == 0x8600 &&
557 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
558 debug("configuring PLX 860X downstream PERST#\n");
559 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
560 dw |= 0xaaa8; /* GPIO1-7 outputs */
561 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
562
563 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
564 dw |= 0xfe; /* GPIO1-7 output high */
565 pci_hose_write_config_dword(hose, dev, 0x644, dw);
566
567 mdelay(100);
568 }
569 }
570 #endif /* CONFIG_CMD_PCI */
571
572 #ifdef CONFIG_SERIAL_TAG
573 /*
574 * called when setting up ATAGS before booting kernel
575 * populate serialnum from the following (in order of priority):
576 * serial# env var
577 * eeprom
578 */
579 void get_board_serial(struct tag_serialnr *serialnr)
580 {
581 char *serial = getenv("serial#");
582
583 if (serial) {
584 serialnr->high = 0;
585 serialnr->low = simple_strtoul(serial, NULL, 10);
586 } else if (ventana_info.model[0]) {
587 serialnr->high = 0;
588 serialnr->low = ventana_info.serial;
589 } else {
590 serialnr->high = 0;
591 serialnr->low = 0;
592 }
593 }
594 #endif
595
596 /*
597 * Board Support
598 */
599
600 int board_early_init_f(void)
601 {
602 setup_iomux_uart();
603
604 #if defined(CONFIG_VIDEO_IPUV3)
605 setup_display();
606 #endif
607 return 0;
608 }
609
610 int dram_init(void)
611 {
612 gd->ram_size = imx_ddr_size();
613 return 0;
614 }
615
616 int board_init(void)
617 {
618 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
619
620 clrsetbits_le32(&iomuxc_regs->gpr[1],
621 IOMUXC_GPR1_OTG_ID_MASK,
622 IOMUXC_GPR1_OTG_ID_GPIO1);
623
624 /* address of linux boot parameters */
625 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
626
627 #ifdef CONFIG_CMD_NAND
628 setup_gpmi_nand();
629 #endif
630 #ifdef CONFIG_MXC_SPI
631 setup_spi();
632 #endif
633 setup_ventana_i2c();
634
635 #ifdef CONFIG_CMD_SATA
636 setup_sata();
637 #endif
638 /* read Gateworks EEPROM into global struct (used later) */
639 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
640
641 setup_iomux_gpio(board_type, &ventana_info);
642
643 return 0;
644 }
645
646 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
647 /*
648 * called during late init (after relocation and after board_init())
649 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
650 * EEPROM read.
651 */
652 int checkboard(void)
653 {
654 struct ventana_board_info *info = &ventana_info;
655 unsigned char buf[4];
656 const char *p;
657 int quiet; /* Quiet or minimal output mode */
658
659 quiet = 0;
660 p = getenv("quiet");
661 if (p)
662 quiet = simple_strtol(p, NULL, 10);
663 else
664 setenv("quiet", "0");
665
666 puts("\nGateworks Corporation Copyright 2014\n");
667 if (info->model[0]) {
668 printf("Model: %s\n", info->model);
669 printf("MFGDate: %02x-%02x-%02x%02x\n",
670 info->mfgdate[0], info->mfgdate[1],
671 info->mfgdate[2], info->mfgdate[3]);
672 printf("Serial:%d\n", info->serial);
673 } else {
674 puts("Invalid EEPROM - board will not function fully\n");
675 }
676 if (quiet)
677 return 0;
678
679 /* Display GSC firmware revision/CRC/status */
680 gsc_info(0);
681
682 /* Display RTC */
683 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
684 printf("RTC: %d\n",
685 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
686 }
687
688 return 0;
689 }
690 #endif
691
692 #ifdef CONFIG_CMD_BMODE
693 /*
694 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
695 * see Table 8-11 and Table 5-9
696 * BOOT_CFG1[7] = 1 (boot from NAND)
697 * BOOT_CFG1[5] = 0 - raw NAND
698 * BOOT_CFG1[4] = 0 - default pad settings
699 * BOOT_CFG1[3:2] = 00 - devices = 1
700 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
701 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
702 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
703 * BOOT_CFG2[0] = 0 - Reset time 12ms
704 */
705 static const struct boot_mode board_boot_modes[] = {
706 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
707 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
708 { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
709 { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/GW5904 */
710 { NULL, 0 },
711 };
712 #endif
713
714 /* late init */
715 int misc_init_r(void)
716 {
717 struct ventana_board_info *info = &ventana_info;
718 char buf[256];
719 int i;
720
721 /* set env vars based on EEPROM data */
722 if (ventana_info.model[0]) {
723 char str[16], fdt[36];
724 char *p;
725 const char *cputype = "";
726
727 /*
728 * FDT name will be prefixed with CPU type. Three versions
729 * will be created each increasingly generic and bootloader
730 * env scripts will try loading each from most specific to
731 * least.
732 */
733 if (is_cpu_type(MXC_CPU_MX6Q) ||
734 is_cpu_type(MXC_CPU_MX6D))
735 cputype = "imx6q";
736 else if (is_cpu_type(MXC_CPU_MX6DL) ||
737 is_cpu_type(MXC_CPU_MX6SOLO))
738 cputype = "imx6dl";
739 setenv("soctype", cputype);
740 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
741 setenv("flash_layout", "large");
742 else
743 setenv("flash_layout", "normal");
744 memset(str, 0, sizeof(str));
745 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
746 str[i] = tolower(info->model[i]);
747 setenv("model", str);
748 if (!getenv("fdt_file")) {
749 sprintf(fdt, "%s-%s.dtb", cputype, str);
750 setenv("fdt_file", fdt);
751 }
752 p = strchr(str, '-');
753 if (p) {
754 *p++ = 0;
755
756 setenv("model_base", str);
757 sprintf(fdt, "%s-%s.dtb", cputype, str);
758 setenv("fdt_file1", fdt);
759 if (board_type != GW551x &&
760 board_type != GW552x &&
761 board_type != GW553x &&
762 board_type != GW560x)
763 str[4] = 'x';
764 str[5] = 'x';
765 str[6] = 0;
766 sprintf(fdt, "%s-%s.dtb", cputype, str);
767 setenv("fdt_file2", fdt);
768 }
769
770 /* initialize env from EEPROM */
771 if (test_bit(EECONFIG_ETH0, info->config) &&
772 !getenv("ethaddr")) {
773 eth_setenv_enetaddr("ethaddr", info->mac0);
774 }
775 if (test_bit(EECONFIG_ETH1, info->config) &&
776 !getenv("eth1addr")) {
777 eth_setenv_enetaddr("eth1addr", info->mac1);
778 }
779
780 /* board serial-number */
781 sprintf(str, "%6d", info->serial);
782 setenv("serial#", str);
783
784 /* memory MB */
785 sprintf(str, "%d", (int) (gd->ram_size >> 20));
786 setenv("mem_mb", str);
787 }
788
789 /* Set a non-initialized hwconfig based on board configuration */
790 if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) {
791 buf[0] = 0;
792 if (gpio_cfg[board_type].rs232_en)
793 strcat(buf, "rs232;");
794 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
795 char buf1[32];
796 sprintf(buf1, "dio%d:mode=gpio;", i);
797 if (strlen(buf) + strlen(buf1) < sizeof(buf))
798 strcat(buf, buf1);
799 }
800 setenv("hwconfig", buf);
801 }
802
803 /* setup baseboard specific GPIO based on board and env */
804 setup_board_gpio(board_type, info);
805
806 #ifdef CONFIG_CMD_BMODE
807 add_board_boot_modes(board_boot_modes);
808 #endif
809
810 /* disable boot watchdog */
811 gsc_boot_wd_disable();
812
813 return 0;
814 }
815
816 #ifdef CONFIG_OF_BOARD_SETUP
817
818 static int ft_sethdmiinfmt(void *blob, char *mode)
819 {
820 int off;
821
822 if (!mode)
823 return -EINVAL;
824
825 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
826 if (off < 0)
827 return off;
828
829 if (0 == strcasecmp(mode, "yuv422bt656")) {
830 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
831 0x00, 0x00, 0x00 };
832 mode = "422_ccir";
833 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
834 fdt_setprop_u32(blob, off, "vidout_trc", 1);
835 fdt_setprop_u32(blob, off, "vidout_blc", 1);
836 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
837 printf(" set HDMI input mode to %s\n", mode);
838 } else if (0 == strcasecmp(mode, "yuv422smp")) {
839 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
840 0x82, 0x81, 0x00 };
841 mode = "422_smp";
842 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
843 fdt_setprop_u32(blob, off, "vidout_trc", 0);
844 fdt_setprop_u32(blob, off, "vidout_blc", 0);
845 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
846 printf(" set HDMI input mode to %s\n", mode);
847 } else {
848 return -EINVAL;
849 }
850
851 return 0;
852 }
853
854 /* enable a property of a node if the node is found */
855 static inline void ft_enable_path(void *blob, const char *path)
856 {
857 int i = fdt_path_offset(blob, path);
858 if (i >= 0) {
859 debug("enabling %s\n", path);
860 fdt_status_okay(blob, i);
861 }
862 }
863
864 /* remove a property of a node if the node is found */
865 static inline void ft_delprop_path(void *blob, const char *path,
866 const char *name)
867 {
868 int i = fdt_path_offset(blob, path);
869 if (i) {
870 debug("removing %s/%s\n", path, name);
871 fdt_delprop(blob, i, name);
872 }
873 }
874
875 #if defined(CONFIG_CMD_PCI)
876 #define PCI_ID(x) ( \
877 (PCI_BUS(x->devfn)<<16)| \
878 (PCI_DEV(x->devfn)<<11)| \
879 (PCI_FUNC(x->devfn)<<8) \
880 )
881 #define PCIE_PATH "/soc/pcie@0x01000000"
882 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
883 {
884 uint32_t reg[5];
885 char node[32];
886 int np;
887
888 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
889 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
890
891 np = fdt_subnode_offset(blob, par, node);
892 if (np >= 0)
893 return np;
894 np = fdt_add_subnode(blob, par, node);
895 if (np < 0) {
896 printf(" %s failed: no space\n", __func__);
897 return np;
898 }
899
900 memset(reg, 0, sizeof(reg));
901 reg[0] = cpu_to_fdt32(PCI_ID(dev));
902 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
903
904 return np;
905 }
906
907 /* build a path of nested PCI devs for all bridges passed through */
908 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
909 {
910 struct pci_dev *bridges[MAX_PCI_DEVS];
911 int k, np;
912
913 /* build list of parents */
914 np = fdt_path_offset(blob, PCIE_PATH);
915 if (np < 0)
916 return np;
917
918 k = 0;
919 while (dev) {
920 bridges[k++] = dev;
921 dev = dev->ppar;
922 };
923
924 /* now add them the to DT in reverse order */
925 while (k--) {
926 np = fdt_add_pci_node(blob, np, bridges[k]);
927 if (np < 0)
928 break;
929 }
930
931 return np;
932 }
933
934 /*
935 * The GW16082 has a hardware errata errata such that it's
936 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
937 * of this normal PCI interrupt swizzling will not work so we will
938 * provide an irq-map via device-tree.
939 */
940 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
941 {
942 int len;
943 int host;
944 uint32_t imap_new[8*4*4];
945 const uint32_t *imap;
946 uint32_t irq[4];
947 uint32_t reg[4];
948 int i;
949
950 /* build irq-map based on host controllers map */
951 host = fdt_path_offset(blob, PCIE_PATH);
952 if (host < 0) {
953 printf(" %s failed: missing host\n", __func__);
954 return host;
955 }
956
957 /* use interrupt data from root complex's node */
958 imap = fdt_getprop(blob, host, "interrupt-map", &len);
959 if (!imap || len != 128) {
960 printf(" %s failed: invalid interrupt-map\n",
961 __func__);
962 return -FDT_ERR_NOTFOUND;
963 }
964
965 /* obtain irq's of host controller in pin order */
966 for (i = 0; i < 4; i++)
967 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
968
969 /*
970 * determine number of swizzles necessary:
971 * For each bridge we pass through we need to swizzle
972 * the number of the slot we are on.
973 */
974 struct pci_dev *d;
975 int b;
976 b = 0;
977 d = dev->ppar;
978 while(d && d->ppar) {
979 b += PCI_DEV(d->devfn);
980 d = d->ppar;
981 }
982
983 /* create new irq mappings for slots12-15
984 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
985 * J3 AD28 12 INTD INTA
986 * J4 AD29 13 INTC INTD
987 * J5 AD30 14 INTB INTC
988 * J2 AD31 15 INTA INTB
989 */
990 for (i = 0; i < 4; i++) {
991 /* addr matches bus:dev:func */
992 u32 addr = dev->busno << 16 | (12+i) << 11;
993
994 /* default cells from root complex */
995 memcpy(&imap_new[i*32], imap, 128);
996 /* first cell is PCI device address (BDF) */
997 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
998 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
999 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1000 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1001 /* third cell is pin */
1002 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1003 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1004 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1005 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1006 /* sixth cell is relative interrupt */
1007 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1008 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1009 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1010 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1011 }
1012 fdt_setprop(blob, np, "interrupt-map", imap_new,
1013 sizeof(imap_new));
1014 reg[0] = cpu_to_fdt32(0xfff00);
1015 reg[1] = 0;
1016 reg[2] = 0;
1017 reg[3] = cpu_to_fdt32(0x7);
1018 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1019 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1020 fdt_setprop_string(blob, np, "device_type", "pci");
1021 fdt_setprop_cell(blob, np, "#address-cells", 3);
1022 fdt_setprop_cell(blob, np, "#size-cells", 2);
1023 printf(" Added custom interrupt-map for GW16082\n");
1024
1025 return 0;
1026 }
1027
1028 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1029 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1030 {
1031 char *tmp, *end;
1032 char mac[16];
1033 unsigned char mac_addr[6];
1034 int j;
1035
1036 sprintf(mac, "eth1addr");
1037 tmp = getenv(mac);
1038 if (tmp) {
1039 for (j = 0; j < 6; j++) {
1040 mac_addr[j] = tmp ?
1041 simple_strtoul(tmp, &end,16) : 0;
1042 if (tmp)
1043 tmp = (*end) ? end+1 : end;
1044 }
1045 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1046 sizeof(mac_addr));
1047 printf(" Added mac addr for eth1\n");
1048 return 0;
1049 }
1050
1051 return -1;
1052 }
1053
1054 /*
1055 * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1056 * we will walk the PCI bus and add bridge nodes up to the device receiving
1057 * the fixup.
1058 */
1059 void ft_board_pci_fixup(void *blob, bd_t *bd)
1060 {
1061 int i, np;
1062 struct pci_dev *dev;
1063
1064 for (i = 0; i < pci_devno; i++) {
1065 dev = &pci_devs[i];
1066
1067 /*
1068 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1069 * an EEPROM at i2c1-0x50.
1070 */
1071 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1072 (dev->device == 0x8240) &&
1073 (i2c_set_bus_num(1) == 0) &&
1074 (i2c_probe(0x50) == 0))
1075 {
1076 np = fdt_add_pci_path(blob, dev);
1077 if (np > 0)
1078 fdt_fixup_gw16082(blob, np, dev);
1079 }
1080
1081 /* ethernet1 mac address */
1082 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1083 (dev->device == 0x4380))
1084 {
1085 np = fdt_add_pci_path(blob, dev);
1086 if (np > 0)
1087 fdt_fixup_sky2(blob, np, dev);
1088 }
1089 }
1090 }
1091 #endif /* if defined(CONFIG_CMD_PCI) */
1092
1093 void ft_board_wdog_fixup(void *blob, const char *path)
1094 {
1095 ft_delprop_path(blob, path, "ext-reset-output");
1096 ft_delprop_path(blob, path, "fsl,ext-reset-output");
1097 }
1098
1099 /*
1100 * called prior to booting kernel or by 'fdt boardsetup' command
1101 *
1102 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1103 * - mtd partitions based on mtdparts/mtdids env
1104 * - system-serial (board serial num from EEPROM)
1105 * - board (full model from EEPROM)
1106 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1107 */
1108 #define UART1_PATH "/soc/aips-bus@02100000/serial@021ec000"
1109 #define WDOG1_PATH "/soc/aips-bus@02000000/wdog@020bc000"
1110 #define WDOG2_PATH "/soc/aips-bus@02000000/wdog@020c0000"
1111 #define GPIO3_PATH "/soc/aips-bus@02000000/gpio@020a4000"
1112 int ft_board_setup(void *blob, bd_t *bd)
1113 {
1114 struct ventana_board_info *info = &ventana_info;
1115 struct ventana_eeprom_config *cfg;
1116 struct node_info nodes[] = {
1117 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1118 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1119 };
1120 const char *model = getenv("model");
1121 const char *display = getenv("display");
1122 int i;
1123 char rev = 0;
1124
1125 /* determine board revision */
1126 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1127 if (ventana_info.model[i] >= 'A') {
1128 rev = ventana_info.model[i];
1129 break;
1130 }
1131 }
1132
1133 if (getenv("fdt_noauto")) {
1134 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1135 return 0;
1136 }
1137
1138 if (test_bit(EECONFIG_NAND, info->config)) {
1139 /* Update partition nodes using info from mtdparts env var */
1140 puts(" Updating MTD partitions...\n");
1141 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1142 }
1143
1144 /* Update display timings from display env var */
1145 if (display) {
1146 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1147 display) >= 0)
1148 printf(" Set display timings for %s...\n", display);
1149 }
1150
1151 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1152
1153 /* board serial number */
1154 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1155 strlen(getenv("serial#")) + 1);
1156
1157 /* board (model contains model from device-tree) */
1158 fdt_setprop(blob, 0, "board", info->model,
1159 strlen((const char *)info->model) + 1);
1160
1161 /* set desired digital video capture format */
1162 ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
1163
1164 /*
1165 * Board model specific fixups
1166 */
1167 switch (board_type) {
1168 case GW51xx:
1169 /*
1170 * disable wdog node for GW51xx-A/B to work around
1171 * errata causing wdog timer to be unreliable.
1172 */
1173 if (rev >= 'A' && rev < 'C') {
1174 i = fdt_path_offset(blob, WDOG1_PATH);
1175 if (i)
1176 fdt_status_disabled(blob, i);
1177 }
1178
1179 /* GW51xx-E adds WDOG1_B external reset */
1180 if (rev < 'E')
1181 ft_board_wdog_fixup(blob, WDOG1_PATH);
1182 break;
1183
1184 case GW52xx:
1185 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1186 if (info->model[4] == '2') {
1187 u32 handle = 0;
1188 u32 *range = NULL;
1189
1190 i = fdt_node_offset_by_compatible(blob, -1,
1191 "fsl,imx6q-pcie");
1192 if (i)
1193 range = (u32 *)fdt_getprop(blob, i,
1194 "reset-gpio", NULL);
1195
1196 if (range) {
1197 i = fdt_path_offset(blob, GPIO3_PATH);
1198 if (i)
1199 handle = fdt_get_phandle(blob, i);
1200 if (handle) {
1201 range[0] = cpu_to_fdt32(handle);
1202 range[1] = cpu_to_fdt32(23);
1203 }
1204 }
1205
1206 /* these have broken usd_vsel */
1207 if (strstr((const char *)info->model, "SP318-B") ||
1208 strstr((const char *)info->model, "SP331-B"))
1209 gpio_cfg[board_type].usd_vsel = 0;
1210
1211 /* GW522x-B adds WDOG1_B external reset */
1212 ft_board_wdog_fixup(blob, WDOG1_PATH);
1213 }
1214
1215 /* GW520x-E adds WDOG1_B external reset */
1216 else if (info->model[4] == '0' && rev < 'E')
1217 ft_board_wdog_fixup(blob, WDOG1_PATH);
1218 break;
1219
1220 case GW53xx:
1221 /* GW53xx-E adds WDOG1_B external reset */
1222 if (rev < 'E')
1223 ft_board_wdog_fixup(blob, WDOG1_PATH);
1224 break;
1225
1226 case GW54xx:
1227 /*
1228 * disable serial2 node for GW54xx for compatibility with older
1229 * 3.10.x kernel that improperly had this node enabled in the DT
1230 */
1231 i = fdt_path_offset(blob, UART1_PATH);
1232 if (i)
1233 fdt_del_node(blob, i);
1234
1235 /* GW54xx-E adds WDOG2_B external reset */
1236 if (rev < 'E')
1237 ft_board_wdog_fixup(blob, WDOG2_PATH);
1238 break;
1239
1240 case GW551x:
1241 /*
1242 * isolate CSI0_DATA_EN for GW551x-A to work around errata
1243 * causing non functional digital video in (it is not hooked up)
1244 */
1245 if (rev == 'A') {
1246 u32 *range = NULL;
1247 int len;
1248 const u32 *handle = NULL;
1249
1250 i = fdt_node_offset_by_compatible(blob, -1,
1251 "fsl,imx-tda1997x-video");
1252 if (i)
1253 handle = fdt_getprop(blob, i, "pinctrl-0",
1254 NULL);
1255 if (handle)
1256 i = fdt_node_offset_by_phandle(blob,
1257 fdt32_to_cpu(*handle));
1258 if (i)
1259 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1260 &len);
1261 if (range) {
1262 len /= sizeof(u32);
1263 for (i = 0; i < len; i += 6) {
1264 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1265 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1266 /* mux PAD_CSI0_DATA_EN to GPIO */
1267 if (is_cpu_type(MXC_CPU_MX6Q) &&
1268 mux_reg == 0x260 &&
1269 conf_reg == 0x630)
1270 range[i+3] = cpu_to_fdt32(0x5);
1271 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1272 mux_reg == 0x08c &&
1273 conf_reg == 0x3a0)
1274 range[i+3] = cpu_to_fdt32(0x5);
1275 }
1276 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1277 len);
1278 }
1279
1280 /* set BT656 video format */
1281 ft_sethdmiinfmt(blob, "yuv422bt656");
1282 }
1283
1284 /* GW551x-C adds WDOG1_B external reset */
1285 if (rev < 'C')
1286 ft_board_wdog_fixup(blob, WDOG1_PATH);
1287 break;
1288 }
1289
1290 /* Configure DIO */
1291 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1292 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1293 char arg[10];
1294
1295 sprintf(arg, "dio%d", i);
1296 if (!hwconfig(arg))
1297 continue;
1298 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1299 {
1300 char path[48];
1301 sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
1302 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
1303 printf(" Enabling pwm%d for DIO%d\n",
1304 cfg->pwm_param, i);
1305 ft_enable_path(blob, path);
1306 }
1307 }
1308
1309 /* remove no-1-8-v if UHS-I support is present */
1310 if (gpio_cfg[board_type].usd_vsel) {
1311 debug("Enabling UHS-I support\n");
1312 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
1313 "no-1-8-v");
1314 }
1315
1316 #if defined(CONFIG_CMD_PCI)
1317 if (!getenv("nopcifixup"))
1318 ft_board_pci_fixup(blob, bd);
1319 #endif
1320
1321 /*
1322 * Peripheral Config:
1323 * remove nodes by alias path if EEPROM config tells us the
1324 * peripheral is not loaded on the board.
1325 */
1326 if (getenv("fdt_noconfig")) {
1327 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1328 return 0;
1329 }
1330 cfg = econfig;
1331 while (cfg->name) {
1332 if (!test_bit(cfg->bit, info->config)) {
1333 fdt_del_node_and_alias(blob, cfg->dtalias ?
1334 cfg->dtalias : cfg->name);
1335 }
1336 cfg++;
1337 }
1338
1339 return 0;
1340 }
1341 #endif /* CONFIG_OF_BOARD_SETUP */
1342
1343 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1344 .reg = (struct mxc_uart *)UART2_BASE,
1345 };
1346
1347 U_BOOT_DEVICE(ventana_serial) = {
1348 .name = "serial_mxc",
1349 .platdata = &ventana_mxc_serial_plat,
1350 };
"Das U-Boot" Source Tree