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imx: ventana: export backlight gpio after gpio driver is available
[people/ms/u-boot.git] / board / gateworks / gw_ventana / gw_ventana.c
1 /*
2 * Copyright (C) 2013 Gateworks Corporation
3 *
4 * Author: Tim Harvey <tharvey@gateworks.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/gpio.h>
17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/imx-common/sata.h>
19 #include <asm/imx-common/spi.h>
20 #include <asm/imx-common/video.h>
21 #include <asm/io.h>
22 #include <dm.h>
23 #include <dm/platform_data/serial_mxc.h>
24 #include <i2c.h>
25 #include <fdt_support.h>
26 #include <fsl_esdhc.h>
27 #include <jffs2/load_kernel.h>
28 #include <linux/ctype.h>
29 #include <miiphy.h>
30 #include <mtd_node.h>
31 #include <netdev.h>
32 #include <pci.h>
33 #include <power/pmic.h>
34 #include <power/ltc3676_pmic.h>
35 #include <power/pfuze100_pmic.h>
36 #include <fdt_support.h>
37 #include <jffs2/load_kernel.h>
38 #include <spi_flash.h>
39
40 #include "gsc.h"
41 #include "common.h"
42
43 DECLARE_GLOBAL_DATA_PTR;
44
45
46 /*
47 * EEPROM board info struct populated by read_eeprom so that we only have to
48 * read it once.
49 */
50 struct ventana_board_info ventana_info;
51
52 static int board_type;
53
54 /* MMC */
55 static iomux_v3_cfg_t const usdhc3_pads[] = {
56 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
57 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
60 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
62 /* CD */
63 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
64 };
65
66 /* ENET */
67 static iomux_v3_cfg_t const enet_pads[] = {
68 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
76 MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
78 MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
85 MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 /* PHY nRST */
87 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
88 };
89
90 /* NAND */
91 static iomux_v3_cfg_t const nfc_pads[] = {
92 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
97 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
98 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
99 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
100 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
101 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
102 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
103 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
104 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
105 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
106 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
107 };
108
109 #ifdef CONFIG_CMD_NAND
110 static void setup_gpmi_nand(void)
111 {
112 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
113
114 /* config gpmi nand iomux */
115 SETUP_IOMUX_PADS(nfc_pads);
116
117 /* config gpmi and bch clock to 100 MHz */
118 clrsetbits_le32(&mxc_ccm->cs2cdr,
119 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
120 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
121 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
122 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
123 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
124 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
125
126 /* enable gpmi and bch clock gating */
127 setbits_le32(&mxc_ccm->CCGR4,
128 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
129 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
130 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
131 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
132 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
133
134 /* enable apbh clock gating */
135 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
136 }
137 #endif
138
139 static void setup_iomux_enet(int gpio)
140 {
141 SETUP_IOMUX_PADS(enet_pads);
142
143 /* toggle PHY_RST# */
144 gpio_request(gpio, "phy_rst#");
145 gpio_direction_output(gpio, 0);
146 mdelay(2);
147 gpio_set_value(gpio, 1);
148 }
149
150 #ifdef CONFIG_USB_EHCI_MX6
151 static iomux_v3_cfg_t const usb_pads[] = {
152 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
153 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
154 /* OTG PWR */
155 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
156 };
157
158 int board_ehci_hcd_init(int port)
159 {
160 int gpio;
161
162 SETUP_IOMUX_PADS(usb_pads);
163
164 /* Reset USB HUB */
165 switch (board_type) {
166 case GW53xx:
167 case GW552x:
168 gpio = (IMX_GPIO_NR(1, 9));
169 break;
170 case GW54proto:
171 case GW54xx:
172 gpio = (IMX_GPIO_NR(1, 16));
173 break;
174 default:
175 return 0;
176 }
177
178 /* request and toggle hub rst */
179 gpio_request(gpio, "usb_hub_rst#");
180 gpio_direction_output(gpio, 0);
181 mdelay(2);
182 gpio_set_value(gpio, 1);
183
184 return 0;
185 }
186
187 int board_ehci_power(int port, int on)
188 {
189 if (port)
190 return 0;
191 gpio_set_value(GP_USB_OTG_PWR, on);
192 return 0;
193 }
194 #endif /* CONFIG_USB_EHCI_MX6 */
195
196 #ifdef CONFIG_FSL_ESDHC
197 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
198
199 int board_mmc_getcd(struct mmc *mmc)
200 {
201 /* Card Detect */
202 gpio_request(GP_SD3_CD, "sd_cd");
203 gpio_direction_input(GP_SD3_CD);
204 return !gpio_get_value(GP_SD3_CD);
205 }
206
207 int board_mmc_init(bd_t *bis)
208 {
209 /* Only one USDHC controller on Ventana */
210 SETUP_IOMUX_PADS(usdhc3_pads);
211 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
212 usdhc_cfg.max_bus_width = 4;
213
214 return fsl_esdhc_initialize(bis, &usdhc_cfg);
215 }
216 #endif /* CONFIG_FSL_ESDHC */
217
218 #ifdef CONFIG_MXC_SPI
219 iomux_v3_cfg_t const ecspi1_pads[] = {
220 /* SS1 */
221 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
222 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
223 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
224 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
225 };
226
227 int board_spi_cs_gpio(unsigned bus, unsigned cs)
228 {
229 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
230 }
231
232 static void setup_spi(void)
233 {
234 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
235 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
236 SETUP_IOMUX_PADS(ecspi1_pads);
237 }
238 #endif
239
240 /* configure eth0 PHY board-specific LED behavior */
241 int board_phy_config(struct phy_device *phydev)
242 {
243 unsigned short val;
244
245 /* Marvel 88E1510 */
246 if (phydev->phy_id == 0x1410dd1) {
247 /*
248 * Page 3, Register 16: LED[2:0] Function Control Register
249 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
250 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
251 */
252 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
253 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
254 val &= 0xff00;
255 val |= 0x0017;
256 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
257 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
258 }
259
260 if (phydev->drv->config)
261 phydev->drv->config(phydev);
262
263 return 0;
264 }
265
266 int board_eth_init(bd_t *bis)
267 {
268 #ifdef CONFIG_FEC_MXC
269 if (board_type != GW551x && board_type != GW552x) {
270 setup_iomux_enet(GP_PHY_RST);
271 cpu_eth_init(bis);
272 }
273 #endif
274
275 #ifdef CONFIG_E1000
276 e1000_initialize(bis);
277 #endif
278
279 #ifdef CONFIG_CI_UDC
280 /* For otg ethernet*/
281 usb_eth_initialize(bis);
282 #endif
283
284 /* default to the first detected enet dev */
285 if (!getenv("ethprime")) {
286 struct eth_device *dev = eth_get_dev_by_index(0);
287 if (dev) {
288 setenv("ethprime", dev->name);
289 printf("set ethprime to %s\n", getenv("ethprime"));
290 }
291 }
292
293 return 0;
294 }
295
296 #if defined(CONFIG_VIDEO_IPUV3)
297
298 static void enable_hdmi(struct display_info_t const *dev)
299 {
300 imx_enable_hdmi_phy();
301 }
302
303 static int detect_i2c(struct display_info_t const *dev)
304 {
305 return i2c_set_bus_num(dev->bus) == 0 &&
306 i2c_probe(dev->addr) == 0;
307 }
308
309 static void enable_lvds(struct display_info_t const *dev)
310 {
311 struct iomuxc *iomux = (struct iomuxc *)
312 IOMUXC_BASE_ADDR;
313
314 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
315 u32 reg = readl(&iomux->gpr[2]);
316 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
317 writel(reg, &iomux->gpr[2]);
318
319 /* Enable Backlight */
320 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
321 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
322 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
323 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
324 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
325 }
326
327 struct display_info_t const displays[] = {{
328 /* HDMI Output */
329 .bus = -1,
330 .addr = 0,
331 .pixfmt = IPU_PIX_FMT_RGB24,
332 .detect = detect_hdmi,
333 .enable = enable_hdmi,
334 .mode = {
335 .name = "HDMI",
336 .refresh = 60,
337 .xres = 1024,
338 .yres = 768,
339 .pixclock = 15385,
340 .left_margin = 220,
341 .right_margin = 40,
342 .upper_margin = 21,
343 .lower_margin = 7,
344 .hsync_len = 60,
345 .vsync_len = 10,
346 .sync = FB_SYNC_EXT,
347 .vmode = FB_VMODE_NONINTERLACED
348 } }, {
349 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
350 .bus = 2,
351 .addr = 0x4,
352 .pixfmt = IPU_PIX_FMT_LVDS666,
353 .detect = detect_i2c,
354 .enable = enable_lvds,
355 .mode = {
356 .name = "Hannstar-XGA",
357 .refresh = 60,
358 .xres = 1024,
359 .yres = 768,
360 .pixclock = 15385,
361 .left_margin = 220,
362 .right_margin = 40,
363 .upper_margin = 21,
364 .lower_margin = 7,
365 .hsync_len = 60,
366 .vsync_len = 10,
367 .sync = FB_SYNC_EXT,
368 .vmode = FB_VMODE_NONINTERLACED
369 } }, {
370 /* DLC700JMG-T-4 */
371 .bus = 0,
372 .addr = 0,
373 .detect = NULL,
374 .enable = enable_lvds,
375 .pixfmt = IPU_PIX_FMT_LVDS666,
376 .mode = {
377 .name = "DLC700JMGT4",
378 .refresh = 60,
379 .xres = 1024, /* 1024x600active pixels */
380 .yres = 600,
381 .pixclock = 15385, /* 64MHz */
382 .left_margin = 220,
383 .right_margin = 40,
384 .upper_margin = 21,
385 .lower_margin = 7,
386 .hsync_len = 60,
387 .vsync_len = 10,
388 .sync = FB_SYNC_EXT,
389 .vmode = FB_VMODE_NONINTERLACED
390 } }, {
391 /* DLC800FIG-T-3 */
392 .bus = 0,
393 .addr = 0,
394 .detect = NULL,
395 .enable = enable_lvds,
396 .pixfmt = IPU_PIX_FMT_LVDS666,
397 .mode = {
398 .name = "DLC800FIGT3",
399 .refresh = 60,
400 .xres = 1024, /* 1024x768 active pixels */
401 .yres = 768,
402 .pixclock = 15385, /* 64MHz */
403 .left_margin = 220,
404 .right_margin = 40,
405 .upper_margin = 21,
406 .lower_margin = 7,
407 .hsync_len = 60,
408 .vsync_len = 10,
409 .sync = FB_SYNC_EXT,
410 .vmode = FB_VMODE_NONINTERLACED
411 } } };
412 size_t display_count = ARRAY_SIZE(displays);
413
414 static void setup_display(void)
415 {
416 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
417 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
418 int reg;
419
420 enable_ipu_clock();
421 imx_setup_hdmi();
422 /* Turn on LDB0,IPU,IPU DI0 clocks */
423 reg = __raw_readl(&mxc_ccm->CCGR3);
424 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
425 writel(reg, &mxc_ccm->CCGR3);
426
427 /* set LDB0, LDB1 clk select to 011/011 */
428 reg = readl(&mxc_ccm->cs2cdr);
429 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
430 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
431 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
432 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
433 writel(reg, &mxc_ccm->cs2cdr);
434
435 reg = readl(&mxc_ccm->cscmr2);
436 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
437 writel(reg, &mxc_ccm->cscmr2);
438
439 reg = readl(&mxc_ccm->chsccdr);
440 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
441 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
442 writel(reg, &mxc_ccm->chsccdr);
443
444 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
445 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
446 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
447 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
448 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
449 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
450 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
451 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
452 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
453 writel(reg, &iomux->gpr[2]);
454
455 reg = readl(&iomux->gpr[3]);
456 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
457 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
458 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
459 writel(reg, &iomux->gpr[3]);
460
461 /* LVDS Backlight GPIO on LVDS connector - output low */
462 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
463 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
464 }
465 #endif /* CONFIG_VIDEO_IPUV3 */
466
467 /* setup board specific PMIC */
468 int power_init_board(void)
469 {
470 setup_pmic();
471 return 0;
472 }
473
474 #if defined(CONFIG_CMD_PCI)
475 int imx6_pcie_toggle_reset(void)
476 {
477 if (board_type < GW_UNKNOWN) {
478 uint pin = gpio_cfg[board_type].pcie_rst;
479 gpio_request(pin, "pci_rst#");
480 gpio_direction_output(pin, 0);
481 mdelay(50);
482 gpio_direction_output(pin, 1);
483 }
484 return 0;
485 }
486
487 /*
488 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
489 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
490 * properly and assert reset for 100ms.
491 */
492 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
493 unsigned short vendor, unsigned short device,
494 unsigned short class)
495 {
496 u32 dw;
497
498 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
499 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
500 if (vendor == PCI_VENDOR_ID_PLX &&
501 (device & 0xfff0) == 0x8600 &&
502 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
503 debug("configuring PLX 860X downstream PERST#\n");
504 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
505 dw |= 0xaaa8; /* GPIO1-7 outputs */
506 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
507
508 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
509 dw |= 0xfe; /* GPIO1-7 output high */
510 pci_hose_write_config_dword(hose, dev, 0x644, dw);
511
512 mdelay(100);
513 }
514 }
515 #endif /* CONFIG_CMD_PCI */
516
517 #ifdef CONFIG_SERIAL_TAG
518 /*
519 * called when setting up ATAGS before booting kernel
520 * populate serialnum from the following (in order of priority):
521 * serial# env var
522 * eeprom
523 */
524 void get_board_serial(struct tag_serialnr *serialnr)
525 {
526 char *serial = getenv("serial#");
527
528 if (serial) {
529 serialnr->high = 0;
530 serialnr->low = simple_strtoul(serial, NULL, 10);
531 } else if (ventana_info.model[0]) {
532 serialnr->high = 0;
533 serialnr->low = ventana_info.serial;
534 } else {
535 serialnr->high = 0;
536 serialnr->low = 0;
537 }
538 }
539 #endif
540
541 /*
542 * Board Support
543 */
544
545 int board_early_init_f(void)
546 {
547 setup_iomux_uart();
548
549 #if defined(CONFIG_VIDEO_IPUV3)
550 setup_display();
551 #endif
552 return 0;
553 }
554
555 int dram_init(void)
556 {
557 gd->ram_size = imx_ddr_size();
558 return 0;
559 }
560
561 int board_init(void)
562 {
563 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
564
565 clrsetbits_le32(&iomuxc_regs->gpr[1],
566 IOMUXC_GPR1_OTG_ID_MASK,
567 IOMUXC_GPR1_OTG_ID_GPIO1);
568
569 /* address of linux boot parameters */
570 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
571
572 #ifdef CONFIG_CMD_NAND
573 setup_gpmi_nand();
574 #endif
575 #ifdef CONFIG_MXC_SPI
576 setup_spi();
577 #endif
578 setup_ventana_i2c();
579
580 #ifdef CONFIG_CMD_SATA
581 setup_sata();
582 #endif
583 /* read Gateworks EEPROM into global struct (used later) */
584 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
585
586 setup_iomux_gpio(board_type, &ventana_info);
587
588 return 0;
589 }
590
591 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
592 /*
593 * called during late init (after relocation and after board_init())
594 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
595 * EEPROM read.
596 */
597 int checkboard(void)
598 {
599 struct ventana_board_info *info = &ventana_info;
600 unsigned char buf[4];
601 const char *p;
602 int quiet; /* Quiet or minimal output mode */
603
604 quiet = 0;
605 p = getenv("quiet");
606 if (p)
607 quiet = simple_strtol(p, NULL, 10);
608 else
609 setenv("quiet", "0");
610
611 puts("\nGateworks Corporation Copyright 2014\n");
612 if (info->model[0]) {
613 printf("Model: %s\n", info->model);
614 printf("MFGDate: %02x-%02x-%02x%02x\n",
615 info->mfgdate[0], info->mfgdate[1],
616 info->mfgdate[2], info->mfgdate[3]);
617 printf("Serial:%d\n", info->serial);
618 } else {
619 puts("Invalid EEPROM - board will not function fully\n");
620 }
621 if (quiet)
622 return 0;
623
624 /* Display GSC firmware revision/CRC/status */
625 gsc_info(0);
626
627 /* Display RTC */
628 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
629 printf("RTC: %d\n",
630 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
631 }
632
633 return 0;
634 }
635 #endif
636
637 #ifdef CONFIG_CMD_BMODE
638 /*
639 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
640 * see Table 8-11 and Table 5-9
641 * BOOT_CFG1[7] = 1 (boot from NAND)
642 * BOOT_CFG1[5] = 0 - raw NAND
643 * BOOT_CFG1[4] = 0 - default pad settings
644 * BOOT_CFG1[3:2] = 00 - devices = 1
645 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
646 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
647 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
648 * BOOT_CFG2[0] = 0 - Reset time 12ms
649 */
650 static const struct boot_mode board_boot_modes[] = {
651 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
652 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
653 { NULL, 0 },
654 };
655 #endif
656
657 /* late init */
658 int misc_init_r(void)
659 {
660 struct ventana_board_info *info = &ventana_info;
661
662 /* set env vars based on EEPROM data */
663 if (ventana_info.model[0]) {
664 char str[16], fdt[36];
665 char *p;
666 const char *cputype = "";
667 int i;
668
669 /*
670 * FDT name will be prefixed with CPU type. Three versions
671 * will be created each increasingly generic and bootloader
672 * env scripts will try loading each from most specific to
673 * least.
674 */
675 if (is_cpu_type(MXC_CPU_MX6Q) ||
676 is_cpu_type(MXC_CPU_MX6D))
677 cputype = "imx6q";
678 else if (is_cpu_type(MXC_CPU_MX6DL) ||
679 is_cpu_type(MXC_CPU_MX6SOLO))
680 cputype = "imx6dl";
681 setenv("soctype", cputype);
682 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
683 setenv("flash_layout", "large");
684 else
685 setenv("flash_layout", "normal");
686 memset(str, 0, sizeof(str));
687 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
688 str[i] = tolower(info->model[i]);
689 setenv("model", str);
690 if (!getenv("fdt_file")) {
691 sprintf(fdt, "%s-%s.dtb", cputype, str);
692 setenv("fdt_file", fdt);
693 }
694 p = strchr(str, '-');
695 if (p) {
696 *p++ = 0;
697
698 setenv("model_base", str);
699 sprintf(fdt, "%s-%s.dtb", cputype, str);
700 setenv("fdt_file1", fdt);
701 if (board_type != GW551x && board_type != GW552x)
702 str[4] = 'x';
703 str[5] = 'x';
704 str[6] = 0;
705 sprintf(fdt, "%s-%s.dtb", cputype, str);
706 setenv("fdt_file2", fdt);
707 }
708
709 /* initialize env from EEPROM */
710 if (test_bit(EECONFIG_ETH0, info->config) &&
711 !getenv("ethaddr")) {
712 eth_setenv_enetaddr("ethaddr", info->mac0);
713 }
714 if (test_bit(EECONFIG_ETH1, info->config) &&
715 !getenv("eth1addr")) {
716 eth_setenv_enetaddr("eth1addr", info->mac1);
717 }
718
719 /* board serial-number */
720 sprintf(str, "%6d", info->serial);
721 setenv("serial#", str);
722
723 /* memory MB */
724 sprintf(str, "%d", (int) (gd->ram_size >> 20));
725 setenv("mem_mb", str);
726 }
727
728
729 /* setup baseboard specific GPIO based on board and env */
730 setup_board_gpio(board_type, info);
731
732 #ifdef CONFIG_CMD_BMODE
733 add_board_boot_modes(board_boot_modes);
734 #endif
735
736 /* disable boot watchdog */
737 gsc_boot_wd_disable();
738
739 return 0;
740 }
741
742 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
743
744 static int ft_sethdmiinfmt(void *blob, char *mode)
745 {
746 int off;
747
748 if (!mode)
749 return -EINVAL;
750
751 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
752 if (off < 0)
753 return off;
754
755 if (0 == strcasecmp(mode, "yuv422bt656")) {
756 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
757 0x00, 0x00, 0x00 };
758 mode = "422_ccir";
759 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
760 fdt_setprop_u32(blob, off, "vidout_trc", 1);
761 fdt_setprop_u32(blob, off, "vidout_blc", 1);
762 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
763 printf(" set HDMI input mode to %s\n", mode);
764 } else if (0 == strcasecmp(mode, "yuv422smp")) {
765 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
766 0x82, 0x81, 0x00 };
767 mode = "422_smp";
768 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
769 fdt_setprop_u32(blob, off, "vidout_trc", 0);
770 fdt_setprop_u32(blob, off, "vidout_blc", 0);
771 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
772 printf(" set HDMI input mode to %s\n", mode);
773 } else {
774 return -EINVAL;
775 }
776
777 return 0;
778 }
779
780 /*
781 * called prior to booting kernel or by 'fdt boardsetup' command
782 *
783 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
784 * - mtd partitions based on mtdparts/mtdids env
785 * - system-serial (board serial num from EEPROM)
786 * - board (full model from EEPROM)
787 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
788 */
789 int ft_board_setup(void *blob, bd_t *bd)
790 {
791 struct ventana_board_info *info = &ventana_info;
792 struct ventana_eeprom_config *cfg;
793 struct node_info nodes[] = {
794 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
795 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
796 };
797 const char *model = getenv("model");
798 const char *display = getenv("display");
799 int i;
800 char rev = 0;
801
802 /* determine board revision */
803 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
804 if (ventana_info.model[i] >= 'A') {
805 rev = ventana_info.model[i];
806 break;
807 }
808 }
809
810 if (getenv("fdt_noauto")) {
811 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
812 return 0;
813 }
814
815 if (test_bit(EECONFIG_NAND, info->config)) {
816 /* Update partition nodes using info from mtdparts env var */
817 puts(" Updating MTD partitions...\n");
818 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
819 }
820
821 /* Update display timings from display env var */
822 if (display) {
823 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
824 display) >= 0)
825 printf(" Set display timings for %s...\n", display);
826 }
827
828 printf(" Adjusting FDT per EEPROM for %s...\n", model);
829
830 /* board serial number */
831 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
832 strlen(getenv("serial#")) + 1);
833
834 /* board (model contains model from device-tree) */
835 fdt_setprop(blob, 0, "board", info->model,
836 strlen((const char *)info->model) + 1);
837
838 /* set desired digital video capture format */
839 ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
840
841 /*
842 * disable serial2 node for GW54xx for compatibility with older
843 * 3.10.x kernel that improperly had this node enabled in the DT
844 */
845 if (board_type == GW54xx) {
846 i = fdt_path_offset(blob,
847 "/soc/aips-bus@02100000/serial@021ec000");
848 if (i)
849 fdt_del_node(blob, i);
850 }
851
852 /*
853 * disable wdog1/wdog2 nodes for GW51xx below revC to work around
854 * errata causing wdog timer to be unreliable.
855 */
856 if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
857 i = fdt_path_offset(blob,
858 "/soc/aips-bus@02000000/wdog@020bc000");
859 if (i)
860 fdt_status_disabled(blob, i);
861 }
862
863 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
864 else if (board_type == GW52xx && info->model[4] == '2') {
865 u32 handle = 0;
866 u32 *range = NULL;
867
868 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
869 if (i)
870 range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
871 NULL);
872
873 if (range) {
874 i = fdt_path_offset(blob,
875 "/soc/aips-bus@02000000/gpio@020a4000");
876 if (i)
877 handle = fdt_get_phandle(blob, i);
878 if (handle) {
879 range[0] = cpu_to_fdt32(handle);
880 range[1] = cpu_to_fdt32(23);
881 }
882 }
883 }
884
885 /*
886 * isolate CSI0_DATA_EN for GW551x below revB to work around
887 * errata causing non functional digital video in (it is not hooked up)
888 */
889 else if (board_type == GW551x && rev == 'A') {
890 u32 *range = NULL;
891 int len;
892 const u32 *handle = NULL;
893
894 i = fdt_node_offset_by_compatible(blob, -1,
895 "fsl,imx-tda1997x-video");
896 if (i)
897 handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
898 if (handle)
899 i = fdt_node_offset_by_phandle(blob,
900 fdt32_to_cpu(*handle));
901 if (i)
902 range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
903 if (range) {
904 len /= sizeof(u32);
905 for (i = 0; i < len; i += 6) {
906 u32 mux_reg = fdt32_to_cpu(range[i+0]);
907 u32 conf_reg = fdt32_to_cpu(range[i+1]);
908 /* mux PAD_CSI0_DATA_EN to GPIO */
909 if (is_cpu_type(MXC_CPU_MX6Q) &&
910 mux_reg == 0x260 && conf_reg == 0x630)
911 range[i+3] = cpu_to_fdt32(0x5);
912 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
913 mux_reg == 0x08c && conf_reg == 0x3a0)
914 range[i+3] = cpu_to_fdt32(0x5);
915 }
916 fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
917 }
918
919 /* set BT656 video format */
920 ft_sethdmiinfmt(blob, "yuv422bt656");
921 }
922
923 /*
924 * Peripheral Config:
925 * remove nodes by alias path if EEPROM config tells us the
926 * peripheral is not loaded on the board.
927 */
928 if (getenv("fdt_noconfig")) {
929 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
930 return 0;
931 }
932 cfg = econfig;
933 while (cfg->name) {
934 if (!test_bit(cfg->bit, info->config)) {
935 fdt_del_node_and_alias(blob, cfg->dtalias ?
936 cfg->dtalias : cfg->name);
937 }
938 cfg++;
939 }
940
941 return 0;
942 }
943 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
944
945 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
946 .reg = (struct mxc_uart *)UART2_BASE,
947 };
948
949 U_BOOT_DEVICE(ventana_serial) = {
950 .name = "serial_mxc",
951 .platdata = &ventana_mxc_serial_plat,
952 };
"Das U-Boot" Source Tree