2 * Copyright (C) 2014 Gateworks Corporation
3 * Author: Tim Harvey <tharvey@gateworks.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-ddr.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/imx-common/boot_mode.h>
16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/imx-common/mxc_i2c.h>
20 #include "ventana_eeprom.h"
22 DECLARE_GLOBAL_DATA_PTR
;
24 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
26 #define GSC_EEPROM_ADDR 0x51
27 #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
28 #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
29 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
30 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
31 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
32 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
33 #define CONFIG_SYS_I2C_SPEED 100000
36 static struct i2c_pads_info mx6q_i2c_pad_info0
= {
38 .i2c_mode
= MX6Q_PAD_EIM_D21__I2C1_SCL
| PC
,
39 .gpio_mode
= MX6Q_PAD_EIM_D21__GPIO3_IO21
| PC
,
40 .gp
= IMX_GPIO_NR(3, 21)
43 .i2c_mode
= MX6Q_PAD_EIM_D28__I2C1_SDA
| PC
,
44 .gpio_mode
= MX6Q_PAD_EIM_D28__GPIO3_IO28
| PC
,
45 .gp
= IMX_GPIO_NR(3, 28)
48 static struct i2c_pads_info mx6dl_i2c_pad_info0
= {
50 .i2c_mode
= MX6DL_PAD_EIM_D21__I2C1_SCL
| PC
,
51 .gpio_mode
= MX6DL_PAD_EIM_D21__GPIO3_IO21
| PC
,
52 .gp
= IMX_GPIO_NR(3, 21)
55 .i2c_mode
= MX6DL_PAD_EIM_D28__I2C1_SDA
| PC
,
56 .gpio_mode
= MX6DL_PAD_EIM_D28__GPIO3_IO28
| PC
,
57 .gp
= IMX_GPIO_NR(3, 28)
61 static void i2c_setup_iomux(void)
63 if (is_cpu_type(MXC_CPU_MX6Q
))
64 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c_pad_info0
);
66 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c_pad_info0
);
69 /* configure MX6Q/DUAL mmdc DDR io registers */
70 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs
= {
71 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
72 .dram_sdclk_0
= 0x00020030,
73 .dram_sdclk_1
= 0x00020030,
74 .dram_cas
= 0x00020030,
75 .dram_ras
= 0x00020030,
76 .dram_reset
= 0x00020030,
77 /* SDCKE[0:1]: 100k pull-up */
78 .dram_sdcke0
= 0x00003000,
79 .dram_sdcke1
= 0x00003000,
80 /* SDBA2: pull-up disabled */
81 .dram_sdba2
= 0x00000000,
82 /* SDODT[0:1]: 100k pull-up, 40 ohm */
83 .dram_sdodt0
= 0x00003030,
84 .dram_sdodt1
= 0x00003030,
85 /* SDQS[0:7]: Differential input, 40 ohm */
86 .dram_sdqs0
= 0x00000030,
87 .dram_sdqs1
= 0x00000030,
88 .dram_sdqs2
= 0x00000030,
89 .dram_sdqs3
= 0x00000030,
90 .dram_sdqs4
= 0x00000030,
91 .dram_sdqs5
= 0x00000030,
92 .dram_sdqs6
= 0x00000030,
93 .dram_sdqs7
= 0x00000030,
95 /* DQM[0:7]: Differential input, 40 ohm */
96 .dram_dqm0
= 0x00020030,
97 .dram_dqm1
= 0x00020030,
98 .dram_dqm2
= 0x00020030,
99 .dram_dqm3
= 0x00020030,
100 .dram_dqm4
= 0x00020030,
101 .dram_dqm5
= 0x00020030,
102 .dram_dqm6
= 0x00020030,
103 .dram_dqm7
= 0x00020030,
106 /* configure MX6Q/DUAL mmdc GRP io registers */
107 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs
= {
109 .grp_ddr_type
= 0x000c0000,
110 .grp_ddrmode_ctl
= 0x00020000,
111 /* disable DDR pullups */
112 .grp_ddrpke
= 0x00000000,
113 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
114 .grp_addds
= 0x00000030,
115 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
116 .grp_ctlds
= 0x00000030,
117 /* DATA[00:63]: Differential input, 40 ohm */
118 .grp_ddrmode
= 0x00020000,
119 .grp_b0ds
= 0x00000030,
120 .grp_b1ds
= 0x00000030,
121 .grp_b2ds
= 0x00000030,
122 .grp_b3ds
= 0x00000030,
123 .grp_b4ds
= 0x00000030,
124 .grp_b5ds
= 0x00000030,
125 .grp_b6ds
= 0x00000030,
126 .grp_b7ds
= 0x00000030,
129 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
130 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs
= {
131 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
132 .dram_sdclk_0
= 0x00020030,
133 .dram_sdclk_1
= 0x00020030,
134 .dram_cas
= 0x00020030,
135 .dram_ras
= 0x00020030,
136 .dram_reset
= 0x00020030,
137 /* SDCKE[0:1]: 100k pull-up */
138 .dram_sdcke0
= 0x00003000,
139 .dram_sdcke1
= 0x00003000,
140 /* SDBA2: pull-up disabled */
141 .dram_sdba2
= 0x00000000,
142 /* SDODT[0:1]: 100k pull-up, 40 ohm */
143 .dram_sdodt0
= 0x00003030,
144 .dram_sdodt1
= 0x00003030,
145 /* SDQS[0:7]: Differential input, 40 ohm */
146 .dram_sdqs0
= 0x00000030,
147 .dram_sdqs1
= 0x00000030,
148 .dram_sdqs2
= 0x00000030,
149 .dram_sdqs3
= 0x00000030,
150 .dram_sdqs4
= 0x00000030,
151 .dram_sdqs5
= 0x00000030,
152 .dram_sdqs6
= 0x00000030,
153 .dram_sdqs7
= 0x00000030,
155 /* DQM[0:7]: Differential input, 40 ohm */
156 .dram_dqm0
= 0x00020030,
157 .dram_dqm1
= 0x00020030,
158 .dram_dqm2
= 0x00020030,
159 .dram_dqm3
= 0x00020030,
160 .dram_dqm4
= 0x00020030,
161 .dram_dqm5
= 0x00020030,
162 .dram_dqm6
= 0x00020030,
163 .dram_dqm7
= 0x00020030,
166 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
167 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
169 .grp_ddr_type
= 0x000c0000,
170 /* SDQS[0:7]: Differential input, 40 ohm */
171 .grp_ddrmode_ctl
= 0x00020000,
172 /* disable DDR pullups */
173 .grp_ddrpke
= 0x00000000,
174 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
175 .grp_addds
= 0x00000030,
176 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
177 .grp_ctlds
= 0x00000030,
178 /* DATA[00:63]: Differential input, 40 ohm */
179 .grp_ddrmode
= 0x00020000,
180 .grp_b0ds
= 0x00000030,
181 .grp_b1ds
= 0x00000030,
182 .grp_b2ds
= 0x00000030,
183 .grp_b3ds
= 0x00000030,
184 .grp_b4ds
= 0x00000030,
185 .grp_b5ds
= 0x00000030,
186 .grp_b6ds
= 0x00000030,
187 .grp_b7ds
= 0x00000030,
190 /* MT41K128M16JT-125 */
191 static struct mx6_ddr3_cfg mt41k128m16jt_125
= {
204 /* MT41K256M16HA-125 */
205 static struct mx6_ddr3_cfg mt41k256m16ha_125
= {
219 * calibration - these are the various CPU/DDR3 combinations we support
222 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib
= {
223 /* write leveling calibration determine */
224 .p0_mpwldectrl0
= 0x00190017,
225 .p0_mpwldectrl1
= 0x00140026,
226 /* Read DQS Gating calibration */
227 .p0_mpdgctrl0
= 0x43380347,
228 .p0_mpdgctrl1
= 0x433C034D,
229 /* Read Calibration: DQS delay relative to DQ read access */
230 .p0_mprddlctl
= 0x3C313539,
231 /* Write Calibration: DQ/DM delay relative to DQS write access */
232 .p0_mpwrdlctl
= 0x36393C39,
235 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib
= {
236 /* write leveling calibration determine */
237 .p0_mpwldectrl0
= 0x003C003C,
238 .p0_mpwldectrl1
= 0x001F002A,
239 /* Read DQS Gating calibration */
240 .p0_mpdgctrl0
= 0x42410244,
241 .p0_mpdgctrl1
= 0x4234023A,
242 /* Read Calibration: DQS delay relative to DQ read access */
243 .p0_mprddlctl
= 0x484A4C4B,
244 /* Write Calibration: DQ/DM delay relative to DQS write access */
245 .p0_mpwrdlctl
= 0x33342B32,
248 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib
= {
249 /* write leveling calibration determine */
250 .p0_mpwldectrl0
= 0x00190017,
251 .p0_mpwldectrl1
= 0x00140026,
252 .p1_mpwldectrl0
= 0x0021001C,
253 .p1_mpwldectrl1
= 0x0011001D,
254 /* Read DQS Gating calibration */
255 .p0_mpdgctrl0
= 0x43380347,
256 .p0_mpdgctrl1
= 0x433C034D,
257 .p1_mpdgctrl0
= 0x032C0324,
258 .p1_mpdgctrl1
= 0x03310232,
259 /* Read Calibration: DQS delay relative to DQ read access */
260 .p0_mprddlctl
= 0x3C313539,
261 .p1_mprddlctl
= 0x37343141,
262 /* Write Calibration: DQ/DM delay relative to DQS write access */
263 .p0_mpwrdlctl
= 0x36393C39,
264 .p1_mpwrdlctl
= 0x42344438,
267 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib
= {
268 /* write leveling calibration determine */
269 .p0_mpwldectrl0
= 0x003C003C,
270 .p0_mpwldectrl1
= 0x001F002A,
271 .p1_mpwldectrl0
= 0x00330038,
272 .p1_mpwldectrl1
= 0x0022003F,
273 /* Read DQS Gating calibration */
274 .p0_mpdgctrl0
= 0x42410244,
275 .p0_mpdgctrl1
= 0x4234023A,
276 .p1_mpdgctrl0
= 0x022D022D,
277 .p1_mpdgctrl1
= 0x021C0228,
278 /* Read Calibration: DQS delay relative to DQ read access */
279 .p0_mprddlctl
= 0x484A4C4B,
280 .p1_mprddlctl
= 0x4B4D4E4B,
281 /* Write Calibration: DQ/DM delay relative to DQS write access */
282 .p0_mpwrdlctl
= 0x33342B32,
283 .p1_mpwrdlctl
= 0x3933332B,
286 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib
= {
287 /* write leveling calibration determine */
288 .p0_mpwldectrl0
= 0x001E001A,
289 .p0_mpwldectrl1
= 0x0026001F,
290 /* Read DQS Gating calibration */
291 .p0_mpdgctrl0
= 0x43370349,
292 .p0_mpdgctrl1
= 0x032D0327,
293 /* Read Calibration: DQS delay relative to DQ read access */
294 .p0_mprddlctl
= 0x3D303639,
295 /* Write Calibration: DQ/DM delay relative to DQS write access */
296 .p0_mpwrdlctl
= 0x32363934,
299 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib
= {
300 /* write leveling calibration determine */
301 .p0_mpwldectrl0
= 0X00220021,
302 .p0_mpwldectrl1
= 0X00200030,
303 .p1_mpwldectrl0
= 0X002D0027,
304 .p1_mpwldectrl1
= 0X00150026,
305 /* Read DQS Gating calibration */
306 .p0_mpdgctrl0
= 0x43330342,
307 .p0_mpdgctrl1
= 0x0339034A,
308 .p1_mpdgctrl0
= 0x032F0325,
309 .p1_mpdgctrl1
= 0x032F022E,
310 /* Read Calibration: DQS delay relative to DQ read access */
311 .p0_mprddlctl
= 0X3A2E3437,
312 .p1_mprddlctl
= 0X35312F3F,
313 /* Write Calibration: DQ/DM delay relative to DQS write access */
314 .p0_mpwrdlctl
= 0X33363B37,
315 .p1_mpwrdlctl
= 0X40304239,
318 static void spl_dram_init(int width
, int size_mb
, int board_model
)
320 struct mx6_ddr3_cfg
*mem
= NULL
;
321 struct mx6_mmdc_calibration
*calib
= NULL
;
322 struct mx6_ddr_sysinfo sysinfo
= {
323 /* width of data bus:0=16,1=32,2=64 */
325 /* config for full 4GB range so that get_mem_size() works */
326 .cs_density
= 32, /* 32Gb per CS */
327 /* single chip select */
330 .rtt_wr
= 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
331 #ifdef RTT_NOM_120OHM
332 .rtt_nom
= 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
334 .rtt_nom
= 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
336 .walat
= 1, /* Write additional latency */
337 .ralat
= 5, /* Read additional latency */
338 .mif3_mode
= 3, /* Command prediction working mode */
339 .bi_on
= 1, /* Bank interleaving enabled */
340 .sde_to_rst
= 0x10, /* 14 cycles, 200us (JEDEC default) */
341 .rst_to_cke
= 0x23, /* 33 cycles, 500us (JEDEC default) */
345 * MMDC Calibration requires the following data:
346 * mx6_mmdc_calibration - board-specific calibration (routing delays)
347 * these calibration values depend on board routing, SoC, and DDR
348 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
349 * mx6_ddr_cfg - chip specific timing/layout details
351 if (width
== 32 && size_mb
== 512) {
352 mem
= &mt41k128m16jt_125
;
353 if (is_cpu_type(MXC_CPU_MX6Q
))
354 calib
= &mx6dq_128x32_mmdc_calib
;
356 calib
= &mx6sdl_128x32_mmdc_calib
;
357 debug("2gB density\n");
358 } else if (width
== 64 && size_mb
== 1024) {
359 mem
= &mt41k128m16jt_125
;
360 if (is_cpu_type(MXC_CPU_MX6Q
))
361 calib
= &mx6dq_128x64_mmdc_calib
;
363 calib
= &mx6sdl_128x64_mmdc_calib
;
364 debug("2gB density\n");
365 } else if (width
== 32 && size_mb
== 1024) {
366 mem
= &mt41k256m16ha_125
;
367 if (is_cpu_type(MXC_CPU_MX6Q
))
368 calib
= &mx6dq_256x32_mmdc_calib
;
369 debug("4gB density\n");
370 } else if (width
== 64 && size_mb
== 2048) {
371 mem
= &mt41k256m16ha_125
;
372 if (is_cpu_type(MXC_CPU_MX6Q
))
373 calib
= &mx6dq_256x64_mmdc_calib
;
374 debug("4gB density\n");
378 puts("Error: Invalid Memory Configuration\n");
382 puts("Error: Invalid Board Calibration Configuration\n");
386 if (is_cpu_type(MXC_CPU_MX6Q
))
387 mx6dq_dram_iocfg(width
, &mx6dq_ddr_ioregs
,
390 mx6sdl_dram_iocfg(width
, &mx6sdl_ddr_ioregs
,
392 mx6_dram_cfg(&sysinfo
, calib
, mem
);
396 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
397 * - we have a stack and a place to store GD, both in SRAM
398 * - no variable global data is available
400 void board_init_f(ulong dummy
)
402 struct ventana_board_info ventana_info
;
405 /* setup AIPS and disable watchdog */
408 /* iomux and setup of i2c */
409 board_early_init_f();
415 /* UART clocks enabled and gd valid - init serial console */
416 preloader_console_init();
418 /* read/validate EEPROM info to determine board model and SDRAM cfg */
419 board_model
= read_eeprom(I2C_GSC
, &ventana_info
);
421 /* provide some some default: 32bit 128MB */
422 if (GW_UNKNOWN
== board_model
) {
423 ventana_info
.sdram_width
= 2;
424 ventana_info
.sdram_size
= 3;
427 /* configure MMDC for SDRAM width/size and per-model calibration */
428 spl_dram_init(8 << ventana_info
.sdram_width
,
429 16 << ventana_info
.sdram_size
,
433 memset(__bss_start
, 0, __bss_end
- __bss_start
);
435 /* load/boot image from boot device */
436 board_init_r(NULL
, 0);
439 void reset_cpu(ulong addr
)