board/gateworks/gw_ventana/gw_ventana_spl.c

   1 /*
   2  * Copyright (C) 2014 Gateworks Corporation
   3  * Author: Tim Harvey <tharvey@gateworks.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <i2c.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-ddr.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/imx-common/boot_mode.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/mxc_i2c.h>
  19 #include <spl.h>
  20
  21 #include "ventana_eeprom.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
  26 #define I2C_GSC                 0
  27 #define GSC_EEPROM_ADDR         0x51
  28 #define GSC_EEPROM_DDR_SIZE     0x2B    /* enum (512,1024,2048) MB */
  29 #define GSC_EEPROM_DDR_WIDTH    0x2D    /* enum (32,64) bit */
  30 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  31         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  32         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  33 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  34 #define CONFIG_SYS_I2C_SPEED    100000
  35
  36 /* I2C1: GSC */
  37 static struct i2c_pads_info mx6q_i2c_pad_info0 = {
  38         .scl = {
  39                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
  40                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
  41                 .gp = IMX_GPIO_NR(3, 21)
  42         },
  43         .sda = {
  44                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
  45                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
  46                 .gp = IMX_GPIO_NR(3, 28)
  47         }
  48 };
  49 static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
  50         .scl = {
  51                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
  52                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
  53                 .gp = IMX_GPIO_NR(3, 21)
  54         },
  55         .sda = {
  56                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
  57                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
  58                 .gp = IMX_GPIO_NR(3, 28)
  59         }
  60 };
  61
  62 static void i2c_setup_iomux(void)
  63 {
  64         if (is_cpu_type(MXC_CPU_MX6Q))
  65                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
  66         else
  67                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
  68 }
  69
  70 /* configure MX6Q/DUAL mmdc DDR io registers */
  71 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  72         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  73         .dram_sdclk_0 = 0x00020030,
  74         .dram_sdclk_1 = 0x00020030,
  75         .dram_cas = 0x00020030,
  76         .dram_ras = 0x00020030,
  77         .dram_reset = 0x00020030,
  78         /* SDCKE[0:1]: 100k pull-up */
  79         .dram_sdcke0 = 0x00003000,
  80         .dram_sdcke1 = 0x00003000,
  81         /* SDBA2: pull-up disabled */
  82         .dram_sdba2 = 0x00000000,
  83         /* SDODT[0:1]: 100k pull-up, 40 ohm */
  84         .dram_sdodt0 = 0x00003030,
  85         .dram_sdodt1 = 0x00003030,
  86         /* SDQS[0:7]: Differential input, 40 ohm */
  87         .dram_sdqs0 = 0x00000030,
  88         .dram_sdqs1 = 0x00000030,
  89         .dram_sdqs2 = 0x00000030,
  90         .dram_sdqs3 = 0x00000030,
  91         .dram_sdqs4 = 0x00000030,
  92         .dram_sdqs5 = 0x00000030,
  93         .dram_sdqs6 = 0x00000030,
  94         .dram_sdqs7 = 0x00000030,
  95
  96         /* DQM[0:7]: Differential input, 40 ohm */
  97         .dram_dqm0 = 0x00020030,
  98         .dram_dqm1 = 0x00020030,
  99         .dram_dqm2 = 0x00020030,
 100         .dram_dqm3 = 0x00020030,
 101         .dram_dqm4 = 0x00020030,
 102         .dram_dqm5 = 0x00020030,
 103         .dram_dqm6 = 0x00020030,
 104         .dram_dqm7 = 0x00020030,
 105 };
 106
 107 /* configure MX6Q/DUAL mmdc GRP io registers */
 108 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 109         /* DDR3 */
 110         .grp_ddr_type = 0x000c0000,
 111         .grp_ddrmode_ctl = 0x00020000,
 112         /* disable DDR pullups */
 113         .grp_ddrpke = 0x00000000,
 114         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 115         .grp_addds = 0x00000030,
 116         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 117         .grp_ctlds = 0x00000030,
 118         /* DATA[00:63]: Differential input, 40 ohm */
 119         .grp_ddrmode = 0x00020000,
 120         .grp_b0ds = 0x00000030,
 121         .grp_b1ds = 0x00000030,
 122         .grp_b2ds = 0x00000030,
 123         .grp_b3ds = 0x00000030,
 124         .grp_b4ds = 0x00000030,
 125         .grp_b5ds = 0x00000030,
 126         .grp_b6ds = 0x00000030,
 127         .grp_b7ds = 0x00000030,
 128 };
 129
 130 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 131 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 132         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
 133         .dram_sdclk_0 = 0x00020030,
 134         .dram_sdclk_1 = 0x00020030,
 135         .dram_cas = 0x00020030,
 136         .dram_ras = 0x00020030,
 137         .dram_reset = 0x00020030,
 138         /* SDCKE[0:1]: 100k pull-up */
 139         .dram_sdcke0 = 0x00003000,
 140         .dram_sdcke1 = 0x00003000,
 141         /* SDBA2: pull-up disabled */
 142         .dram_sdba2 = 0x00000000,
 143         /* SDODT[0:1]: 100k pull-up, 40 ohm */
 144         .dram_sdodt0 = 0x00003030,
 145         .dram_sdodt1 = 0x00003030,
 146         /* SDQS[0:7]: Differential input, 40 ohm */
 147         .dram_sdqs0 = 0x00000030,
 148         .dram_sdqs1 = 0x00000030,
 149         .dram_sdqs2 = 0x00000030,
 150         .dram_sdqs3 = 0x00000030,
 151         .dram_sdqs4 = 0x00000030,
 152         .dram_sdqs5 = 0x00000030,
 153         .dram_sdqs6 = 0x00000030,
 154         .dram_sdqs7 = 0x00000030,
 155
 156         /* DQM[0:7]: Differential input, 40 ohm */
 157         .dram_dqm0 = 0x00020030,
 158         .dram_dqm1 = 0x00020030,
 159         .dram_dqm2 = 0x00020030,
 160         .dram_dqm3 = 0x00020030,
 161         .dram_dqm4 = 0x00020030,
 162         .dram_dqm5 = 0x00020030,
 163         .dram_dqm6 = 0x00020030,
 164         .dram_dqm7 = 0x00020030,
 165 };
 166
 167 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 168 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 169         /* DDR3 */
 170         .grp_ddr_type = 0x000c0000,
 171         /* SDQS[0:7]: Differential input, 40 ohm */
 172         .grp_ddrmode_ctl = 0x00020000,
 173         /* disable DDR pullups */
 174         .grp_ddrpke = 0x00000000,
 175         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 176         .grp_addds = 0x00000030,
 177         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 178         .grp_ctlds = 0x00000030,
 179         /* DATA[00:63]: Differential input, 40 ohm */
 180         .grp_ddrmode = 0x00020000,
 181         .grp_b0ds = 0x00000030,
 182         .grp_b1ds = 0x00000030,
 183         .grp_b2ds = 0x00000030,
 184         .grp_b3ds = 0x00000030,
 185         .grp_b4ds = 0x00000030,
 186         .grp_b5ds = 0x00000030,
 187         .grp_b6ds = 0x00000030,
 188         .grp_b7ds = 0x00000030,
 189 };
 190
 191 /* MT41K64M16JT-125 (1Gb density) */
 192 static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
 193         .mem_speed = 1600,
 194         .density = 1,
 195         .width = 16,
 196         .banks = 8,
 197         .rowaddr = 13,
 198         .coladdr = 10,
 199         .pagesz = 2,
 200         .trcd = 1375,
 201         .trcmin = 4875,
 202         .trasmin = 3500,
 203 };
 204
 205 /* MT41K128M16JT-125 (2Gb density) */
 206 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 207         .mem_speed = 1600,
 208         .density = 2,
 209         .width = 16,
 210         .banks = 8,
 211         .rowaddr = 14,
 212         .coladdr = 10,
 213         .pagesz = 2,
 214         .trcd = 1375,
 215         .trcmin = 4875,
 216         .trasmin = 3500,
 217 };
 218
 219 /* MT41K256M16HA-125 (4Gb density) */
 220 static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
 221         .mem_speed = 1600,
 222         .density = 4,
 223         .width = 16,
 224         .banks = 8,
 225         .rowaddr = 15,
 226         .coladdr = 10,
 227         .pagesz = 2,
 228         .trcd = 1375,
 229         .trcmin = 4875,
 230         .trasmin = 3500,
 231 };
 232
 233 /*
 234  * calibration - these are the various CPU/DDR3 combinations we support
 235  */
 236 static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
 237         /* write leveling calibration determine */
 238         .p0_mpwldectrl0 = 0x004C004E,
 239         .p0_mpwldectrl1 = 0x00440044,
 240         /* Read DQS Gating calibration */
 241         .p0_mpdgctrl0 = 0x42440247,
 242         .p0_mpdgctrl1 = 0x02310232,
 243         /* Read Calibration: DQS delay relative to DQ read access */
 244         .p0_mprddlctl = 0x45424746,
 245         /* Write Calibration: DQ/DM delay relative to DQS write access */
 246         .p0_mpwrdlctl = 0x33382C31,
 247 };
 248
 249 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
 250         /* write leveling calibration determine */
 251         .p0_mpwldectrl0 = 0x001B0016,
 252         .p0_mpwldectrl1 = 0x000C000E,
 253         /* Read DQS Gating calibration */
 254         .p0_mpdgctrl0 = 0x4324033A,
 255         .p0_mpdgctrl1 = 0x00000000,
 256         /* Read Calibration: DQS delay relative to DQ read access */
 257         .p0_mprddlctl = 0x40403438,
 258         /* Write Calibration: DQ/DM delay relative to DQS write access */
 259         .p0_mpwrdlctl = 0x40403D36,
 260 };
 261
 262 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
 263         /* write leveling calibration determine */
 264         .p0_mpwldectrl0 = 0x00420043,
 265         .p0_mpwldectrl1 = 0x0016001A,
 266         /* Read DQS Gating calibration */
 267         .p0_mpdgctrl0 = 0x4238023B,
 268         .p0_mpdgctrl1 = 0x00000000,
 269         /* Read Calibration: DQS delay relative to DQ read access */
 270         .p0_mprddlctl = 0x40404849,
 271         /* Write Calibration: DQ/DM delay relative to DQS write access */
 272         .p0_mpwrdlctl = 0x40402E2F,
 273 };
 274
 275 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
 276         /* write leveling calibration determine */
 277         .p0_mpwldectrl0 = 0x00190017,
 278         .p0_mpwldectrl1 = 0x00140026,
 279         /* Read DQS Gating calibration */
 280         .p0_mpdgctrl0 = 0x43380347,
 281         .p0_mpdgctrl1 = 0x433C034D,
 282         /* Read Calibration: DQS delay relative to DQ read access */
 283         .p0_mprddlctl = 0x3C313539,
 284         /* Write Calibration: DQ/DM delay relative to DQS write access */
 285         .p0_mpwrdlctl = 0x36393C39,
 286 };
 287
 288 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
 289         /* write leveling calibration determine */
 290         .p0_mpwldectrl0 = 0x003C003C,
 291         .p0_mpwldectrl1 = 0x001F002A,
 292         /* Read DQS Gating calibration */
 293         .p0_mpdgctrl0 = 0x42410244,
 294         .p0_mpdgctrl1 = 0x4234023A,
 295         /* Read Calibration: DQS delay relative to DQ read access */
 296         .p0_mprddlctl = 0x484A4C4B,
 297         /* Write Calibration: DQ/DM delay relative to DQS write access */
 298         .p0_mpwrdlctl = 0x33342B32,
 299 };
 300
 301 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
 302         /* write leveling calibration determine */
 303         .p0_mpwldectrl0 = 0x00190017,
 304         .p0_mpwldectrl1 = 0x00140026,
 305         .p1_mpwldectrl0 = 0x0021001C,
 306         .p1_mpwldectrl1 = 0x0011001D,
 307         /* Read DQS Gating calibration */
 308         .p0_mpdgctrl0 = 0x43380347,
 309         .p0_mpdgctrl1 = 0x433C034D,
 310         .p1_mpdgctrl0 = 0x032C0324,
 311         .p1_mpdgctrl1 = 0x03310232,
 312         /* Read Calibration: DQS delay relative to DQ read access */
 313         .p0_mprddlctl = 0x3C313539,
 314         .p1_mprddlctl = 0x37343141,
 315         /* Write Calibration: DQ/DM delay relative to DQS write access */
 316         .p0_mpwrdlctl = 0x36393C39,
 317         .p1_mpwrdlctl = 0x42344438,
 318 };
 319
 320 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
 321         /* write leveling calibration determine */
 322         .p0_mpwldectrl0 = 0x003C003C,
 323         .p0_mpwldectrl1 = 0x001F002A,
 324         .p1_mpwldectrl0 = 0x00330038,
 325         .p1_mpwldectrl1 = 0x0022003F,
 326         /* Read DQS Gating calibration */
 327         .p0_mpdgctrl0 = 0x42410244,
 328         .p0_mpdgctrl1 = 0x4234023A,
 329         .p1_mpdgctrl0 = 0x022D022D,
 330         .p1_mpdgctrl1 = 0x021C0228,
 331         /* Read Calibration: DQS delay relative to DQ read access */
 332         .p0_mprddlctl = 0x484A4C4B,
 333         .p1_mprddlctl = 0x4B4D4E4B,
 334         /* Write Calibration: DQ/DM delay relative to DQS write access */
 335         .p0_mpwrdlctl = 0x33342B32,
 336         .p1_mpwrdlctl = 0x3933332B,
 337 };
 338
 339 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
 340         /* write leveling calibration determine */
 341         .p0_mpwldectrl0 = 0x001E001A,
 342         .p0_mpwldectrl1 = 0x0026001F,
 343         /* Read DQS Gating calibration */
 344         .p0_mpdgctrl0 = 0x43370349,
 345         .p0_mpdgctrl1 = 0x032D0327,
 346         /* Read Calibration: DQS delay relative to DQ read access */
 347         .p0_mprddlctl = 0x3D303639,
 348         /* Write Calibration: DQ/DM delay relative to DQS write access */
 349         .p0_mpwrdlctl = 0x32363934,
 350 };
 351
 352 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
 353         /* write leveling calibration determine */
 354         .p0_mpwldectrl0 = 0X00480047,
 355         .p0_mpwldectrl1 = 0X003D003F,
 356         /* Read DQS Gating calibration */
 357         .p0_mpdgctrl0 = 0X423E0241,
 358         .p0_mpdgctrl1 = 0X022B022C,
 359         /* Read Calibration: DQS delay relative to DQ read access */
 360         .p0_mprddlctl = 0X49454A4A,
 361         /* Write Calibration: DQ/DM delay relative to DQS write access */
 362         .p0_mpwrdlctl = 0X2E372C32,
 363 };
 364
 365 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
 366         /* write leveling calibration determine */
 367         .p0_mpwldectrl0 = 0X00220021,
 368         .p0_mpwldectrl1 = 0X00200030,
 369         .p1_mpwldectrl0 = 0X002D0027,
 370         .p1_mpwldectrl1 = 0X00150026,
 371         /* Read DQS Gating calibration */
 372         .p0_mpdgctrl0 = 0x43330342,
 373         .p0_mpdgctrl1 = 0x0339034A,
 374         .p1_mpdgctrl0 = 0x032F0325,
 375         .p1_mpdgctrl1 = 0x032F022E,
 376         /* Read Calibration: DQS delay relative to DQ read access */
 377         .p0_mprddlctl = 0X3A2E3437,
 378         .p1_mprddlctl = 0X35312F3F,
 379         /* Write Calibration: DQ/DM delay relative to DQS write access */
 380         .p0_mpwrdlctl = 0X33363B37,
 381         .p1_mpwrdlctl = 0X40304239,
 382 };
 383
 384 static void spl_dram_init(int width, int size_mb, int board_model)
 385 {
 386         struct mx6_ddr3_cfg *mem = NULL;
 387         struct mx6_mmdc_calibration *calib = NULL;
 388         struct mx6_ddr_sysinfo sysinfo = {
 389                 /* width of data bus:0=16,1=32,2=64 */
 390                 .dsize = width/32,
 391                 /* config for full 4GB range so that get_mem_size() works */
 392                 .cs_density = 32, /* 32Gb per CS */
 393                 /* single chip select */
 394                 .ncs = 1,
 395                 .cs1_mirror = 0,
 396                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 397 #ifdef RTT_NOM_120OHM
 398                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 399 #else
 400                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 401 #endif
 402                 .walat = 1,     /* Write additional latency */
 403                 .ralat = 5,     /* Read additional latency */
 404                 .mif3_mode = 3, /* Command prediction working mode */
 405                 .bi_on = 1,     /* Bank interleaving enabled */
 406                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 407                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 408                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 409         };
 410
 411         /*
 412          * MMDC Calibration requires the following data:
 413          *   mx6_mmdc_calibration - board-specific calibration (routing delays)
 414          *      these calibration values depend on board routing, SoC, and DDR
 415          *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
 416          *   mx6_ddr_cfg - chip specific timing/layout details
 417          */
 418         if (width == 16 && size_mb == 128) {
 419                 mem = &mt41k64m16jt_125;
 420                 if (is_cpu_type(MXC_CPU_MX6Q))
 421                         ;
 422                 else
 423                         calib = &mx6sdl_64x16_mmdc_calib;
 424                 debug("1gB density\n");
 425         } else if (width == 16 && size_mb == 256) {
 426                 /* 1x 2Gb density chip - same calib as 2x 2Gb */
 427                 mem = &mt41k128m16jt_125;
 428                 if (is_cpu_type(MXC_CPU_MX6Q))
 429                         calib = &mx6dq_128x32_mmdc_calib;
 430                 else
 431                         calib = &mx6sdl_128x32_mmdc_calib;
 432                 debug("2gB density\n");
 433         } else if (width == 16 && size_mb == 512) {
 434                 mem = &mt41k256m16ha_125;
 435                 if (is_cpu_type(MXC_CPU_MX6Q))
 436                         calib = &mx6dq_256x16_mmdc_calib;
 437                 else
 438                         calib = &mx6sdl_256x16_mmdc_calib;
 439                 debug("4gB density\n");
 440         } else if (width == 32 && size_mb == 256) {
 441                 /* Same calib as width==16, size==128 */
 442                 mem = &mt41k64m16jt_125;
 443                 if (is_cpu_type(MXC_CPU_MX6Q))
 444                         ;
 445                 else
 446                         calib = &mx6sdl_64x16_mmdc_calib;
 447                 debug("1gB density\n");
 448         } else if (width == 32 && size_mb == 512) {
 449                 mem = &mt41k128m16jt_125;
 450                 if (is_cpu_type(MXC_CPU_MX6Q))
 451                         calib = &mx6dq_128x32_mmdc_calib;
 452                 else
 453                         calib = &mx6sdl_128x32_mmdc_calib;
 454                 debug("2gB density\n");
 455         }  else if (width == 32 && size_mb == 1024) {
 456                 mem = &mt41k256m16ha_125;
 457                 if (is_cpu_type(MXC_CPU_MX6Q))
 458                         calib = &mx6dq_256x32_mmdc_calib;
 459                 else
 460                         calib = &mx6sdl_256x32_mmdc_calib;
 461                 debug("4gB density\n");
 462         } else if (width == 64 && size_mb == 512) {
 463                 mem = &mt41k64m16jt_125;
 464                 debug("1gB density\n");
 465         } else if (width == 64 && size_mb == 1024) {
 466                 mem = &mt41k128m16jt_125;
 467                 if (is_cpu_type(MXC_CPU_MX6Q))
 468                         calib = &mx6dq_128x64_mmdc_calib;
 469                 else
 470                         calib = &mx6sdl_128x64_mmdc_calib;
 471                 debug("2gB density\n");
 472         } else if (width == 64 && size_mb == 2048) {
 473                 mem = &mt41k256m16ha_125;
 474                 if (is_cpu_type(MXC_CPU_MX6Q))
 475                         calib = &mx6dq_256x64_mmdc_calib;
 476                 debug("4gB density\n");
 477         }
 478
 479         if (!(mem && calib)) {
 480                 puts("Error: Invalid Calibration/Board Configuration\n");
 481                 printf("MEM    : %s\n", mem ? "OKAY" : "NULL");
 482                 printf("CALIB  : %s\n", calib ? "OKAY" : "NULL");
 483                 printf("CPUTYPE: %s\n",
 484                        is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
 485                 printf("SIZE_MB: %d\n", size_mb);
 486                 printf("WIDTH  : %d\n", width);
 487                 hang();
 488         }
 489
 490         if (is_cpu_type(MXC_CPU_MX6Q))
 491                 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
 492                                  &mx6dq_grp_ioregs);
 493         else
 494                 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
 495                                   &mx6sdl_grp_ioregs);
 496         mx6_dram_cfg(&sysinfo, calib, mem);
 497 }
 498
 499 static void ccgr_init(void)
 500 {
 501         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 502
 503         writel(0x00C03F3F, &ccm->CCGR0);
 504         writel(0x0030FC03, &ccm->CCGR1);
 505         writel(0x0FFFC000, &ccm->CCGR2);
 506         writel(0x3FF00000, &ccm->CCGR3);
 507         writel(0xFFFFF300, &ccm->CCGR4);        /* enable NAND/GPMI/BCH clks */
 508         writel(0x0F0000C3, &ccm->CCGR5);
 509         writel(0x000003FF, &ccm->CCGR6);
 510 }
 511
 512 static void gpr_init(void)
 513 {
 514         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 515
 516         /* enable AXI cache for VDOA/VPU/IPU */
 517         writel(0xF00000CF, &iomux->gpr[4]);
 518         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 519         writel(0x007F007F, &iomux->gpr[6]);
 520         writel(0x007F007F, &iomux->gpr[7]);
 521 }
 522
 523 /*
 524  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 525  * - we have a stack and a place to store GD, both in SRAM
 526  * - no variable global data is available
 527  */
 528 void board_init_f(ulong dummy)
 529 {
 530         struct ventana_board_info ventana_info;
 531         int board_model;
 532
 533         /* setup AIPS and disable watchdog */
 534         arch_cpu_init();
 535
 536         ccgr_init();
 537         gpr_init();
 538
 539         /* iomux and setup of i2c */
 540         board_early_init_f();
 541         i2c_setup_iomux();
 542
 543         /* setup GP timer */
 544         timer_init();
 545
 546         /* UART clocks enabled and gd valid - init serial console */
 547         preloader_console_init();
 548
 549         /* read/validate EEPROM info to determine board model and SDRAM cfg */
 550         board_model = read_eeprom(I2C_GSC, &ventana_info);
 551
 552         /* provide some some default: 32bit 128MB */
 553         if (GW_UNKNOWN == board_model) {
 554                 ventana_info.sdram_width = 2;
 555                 ventana_info.sdram_size = 3;
 556         }
 557
 558         /* configure MMDC for SDRAM width/size and per-model calibration */
 559         spl_dram_init(8 << ventana_info.sdram_width,
 560                       16 << ventana_info.sdram_size,
 561                       board_model);
 562
 563         /* Clear the BSS. */
 564         memset(__bss_start, 0, __bss_end - __bss_start);
 565
 566         /* load/boot image from boot device */
 567         board_init_r(NULL, 0);
 568 }
 569
 570 void reset_cpu(ulong addr)
 571 {
 572 }