board/gdsys/405ep/dlvision-10g.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <asm/ppc4xx-gpio.h>
  29
  30 #include <gdsys_fpga.h>
  31
  32 #include "../common/osd.h"
  33
  34 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  35 #define LATCH2_MC2_PRESENT_N 0x0080
  36
  37 enum {
  38         UNITTYPE_VIDEO_USER = 0,
  39         UNITTYPE_MAIN_USER = 1,
  40         UNITTYPE_VIDEO_SERVER = 2,
  41         UNITTYPE_MAIN_SERVER = 3,
  42 };
  43
  44 enum {
  45         HWVER_101 = 0,
  46         HWVER_110 = 1,
  47 };
  48
  49 enum {
  50         AUDIO_NONE = 0,
  51         AUDIO_TX = 1,
  52         AUDIO_RX = 2,
  53         AUDIO_RXTX = 3,
  54 };
  55
  56 enum {
  57         SYSCLK_156250 = 2,
  58 };
  59
  60 enum {
  61         RAM_NONE = 0,
  62         RAM_DDR2_32 = 1,
  63         RAM_DDR2_64 = 2,
  64 };
  65
  66 static void print_fpga_info(unsigned dev)
  67 {
  68         ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
  69         u16 versions = in_le16(&fpga->versions);
  70         u16 fpga_version = in_le16(&fpga->fpga_version);
  71         u16 fpga_features = in_le16(&fpga->fpga_features);
  72         unsigned unit_type;
  73         unsigned hardware_version;
  74         unsigned feature_compression;
  75         unsigned feature_rs232;
  76         unsigned feature_audio;
  77         unsigned feature_sysclock;
  78         unsigned feature_ramconfig;
  79         unsigned feature_carrier_speed;
  80         unsigned feature_carriers;
  81         unsigned feature_video_channels;
  82         int fpga_state = get_fpga_state(dev);
  83
  84         printf("FPGA%d: ", dev);
  85
  86         hardware_version = versions & 0x000f;
  87
  88         if (fpga_state
  89             && !((hardware_version == HWVER_101)
  90                  && (fpga_state == FPGA_STATE_DONE_FAILED))) {
  91                 puts("not available\n");
  92                 print_fpga_state(dev);
  93                 return;
  94         }
  95
  96         unit_type = (versions >> 4) & 0x000f;
  97         hardware_version = versions & 0x000f;
  98         feature_compression = (fpga_features >> 13) & 0x0003;
  99         feature_rs232 = fpga_features & (1<<11);
 100         feature_audio = (fpga_features >> 9) & 0x0003;
 101         feature_sysclock = (fpga_features >> 7) & 0x0003;
 102         feature_ramconfig = (fpga_features >> 5) & 0x0003;
 103         feature_carrier_speed = fpga_features & (1<<4);
 104         feature_carriers = (fpga_features >> 2) & 0x0003;
 105         feature_video_channels = fpga_features & 0x0003;
 106
 107         switch (unit_type) {
 108         case UNITTYPE_VIDEO_USER:
 109                 printf("Videochannel Userside");
 110                 break;
 111
 112         case UNITTYPE_MAIN_USER:
 113                 printf("Mainchannel Userside");
 114                 break;
 115
 116         case UNITTYPE_VIDEO_SERVER:
 117                 printf("Videochannel Serverside");
 118                 break;
 119
 120         case UNITTYPE_MAIN_SERVER:
 121                 printf("Mainchannel Serverside");
 122                 break;
 123
 124         default:
 125                 printf("UnitType %d(not supported)", unit_type);
 126                 break;
 127         }
 128
 129         switch (hardware_version) {
 130         case HWVER_101:
 131                 printf(" HW-Ver 1.01\n");
 132                 break;
 133
 134         case HWVER_110:
 135                 printf(" HW-Ver 1.10\n");
 136                 break;
 137
 138         default:
 139                 printf(" HW-Ver %d(not supported)\n",
 140                        hardware_version);
 141                 break;
 142         }
 143
 144         printf("       FPGA V %d.%02d, features:",
 145                 fpga_version / 100, fpga_version % 100);
 146
 147         printf(" %sRS232", feature_rs232 ? "" : "no ");
 148
 149         switch (feature_audio) {
 150         case AUDIO_NONE:
 151                 printf(", no audio");
 152                 break;
 153
 154         case AUDIO_TX:
 155                 printf(", audio tx");
 156                 break;
 157
 158         case AUDIO_RX:
 159                 printf(", audio rx");
 160                 break;
 161
 162         case AUDIO_RXTX:
 163                 printf(", audio rx+tx");
 164                 break;
 165
 166         default:
 167                 printf(", audio %d(not supported)", feature_audio);
 168                 break;
 169         }
 170
 171         switch (feature_sysclock) {
 172         case SYSCLK_156250:
 173                 printf(", clock 156.25 MHz");
 174                 break;
 175
 176         default:
 177                 printf(", clock %d(not supported)", feature_sysclock);
 178                 break;
 179         }
 180
 181         puts(",\n       ");
 182
 183         switch (feature_ramconfig) {
 184         case RAM_NONE:
 185                 printf("no RAM");
 186                 break;
 187
 188         case RAM_DDR2_32:
 189                 printf("RAM 32 bit DDR2");
 190                 break;
 191
 192         case RAM_DDR2_64:
 193                 printf("RAM 64 bit DDR2");
 194                 break;
 195
 196         default:
 197                 printf("RAM %d(not supported)", feature_ramconfig);
 198                 break;
 199         }
 200
 201         printf(", %d carrier(s) %s", feature_carriers,
 202                 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
 203
 204         printf(", %d video channel(s)\n", feature_video_channels);
 205 }
 206
 207 /*
 208  * Check Board Identity:
 209  */
 210 int checkboard(void)
 211 {
 212         char *s = getenv("serial#");
 213         u16 latch2 = in_le16((void *)LATCH2_BASE);
 214
 215         printf("Board: ");
 216
 217         printf("DLVision 10G");
 218
 219         if (s != NULL) {
 220                 puts(", serial# ");
 221                 puts(s);
 222         }
 223
 224         puts("\n");
 225
 226         print_fpga_info(0);
 227         if (!(latch2 & LATCH2_MC2_PRESENT_N))
 228                 print_fpga_info(1);
 229
 230         return 0;
 231 }
 232
 233 int last_stage_init(void)
 234 {
 235         ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 236         u16 versions = in_le16(&fpga->versions);
 237         u16 latch2 = in_le16((void *)LATCH2_BASE);
 238
 239         if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
 240                 return 0;
 241
 242         if (!get_fpga_state(0))
 243                 osd_probe(0);
 244
 245         if (!(latch2 & LATCH2_MC2_PRESENT_N) && !get_fpga_state(1))
 246                 osd_probe(1);
 247
 248         return 0;
 249 }