3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
18 #include <gdsys_fpga.h>
20 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
21 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
22 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
24 #define PHYREG_CONTROL 0
25 #define PHYREG_PAGE_ADDRESS 22
26 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
27 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
30 UNITTYPE_CCD_SWITCH
= 1,
48 int configure_gbit_phy(unsigned char addr
)
53 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
54 PHYREG_PAGE_ADDRESS
, 0x0002))
56 /* disable SGMII autonegotiation */
57 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
58 PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2
, 0x800a))
61 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
62 PHYREG_PAGE_ADDRESS
, 0x0000))
64 /* switch from powerdown to normal operation */
65 if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
66 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1
, &value
))
68 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
69 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1
, value
& ~0x0004))
71 /* reset phy so settings take effect */
72 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
73 PHYREG_CONTROL
, 0x9140))
79 printf("Error writing to the PHY addr=%02x\n", addr
);
84 * Check Board Identity:
88 char *s
= getenv("serial#");
90 puts("Board: CATCenter Io");
102 static void print_fpga_info(void)
104 struct ihs_fpga
*fpga
= (struct ihs_fpga
*) CONFIG_SYS_FPGA_BASE(0);
105 u16 versions
= in_le16(&fpga
->versions
);
106 u16 fpga_version
= in_le16(&fpga
->fpga_version
);
107 u16 fpga_features
= in_le16(&fpga
->fpga_features
);
109 unsigned hardware_version
;
110 unsigned feature_channels
;
111 unsigned feature_expansion
;
113 unit_type
= (versions
& 0xf000) >> 12;
114 hardware_version
= versions
& 0x000f;
115 feature_channels
= fpga_features
& 0x007f;
116 feature_expansion
= fpga_features
& (1<<15);
121 case UNITTYPE_CCD_SWITCH
:
122 printf("CCD-Switch");
126 printf("UnitType %d(not supported)", unit_type
);
130 switch (hardware_version
) {
132 printf(" HW-Ver 1.00\n");
136 printf(" HW-Ver 1.10\n");
140 printf(" HW-Ver 1.21\n");
144 printf(" HW-Ver 1.22\n");
148 printf(" HW-Ver %d(not supported)\n",
153 printf(" FPGA V %d.%02d, features:",
154 fpga_version
/ 100, fpga_version
% 100);
156 printf(" %d channel(s)", feature_channels
);
158 printf(", expansion %ssupported\n", feature_expansion
? "" : "un");
164 int last_stage_init(void)
166 struct ihs_fpga
*fpga
= (struct ihs_fpga
*) CONFIG_SYS_FPGA_BASE(0);
171 miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME
,
172 bb_miiphy_read
, bb_miiphy_write
);
174 for (k
= 0; k
< 32; ++k
)
175 configure_gbit_phy(k
);
177 /* take fpga serdes blocks out of reset */
178 out_le16(&fpga
->quad_serdes_reset
, 0);
183 void gd405ep_init(void)
187 void gd405ep_set_fpga_reset(unsigned state
)
190 out_le16((void *)LATCH0_BASE
, CONFIG_SYS_LATCH0_RESET
);
191 out_le16((void *)LATCH1_BASE
, CONFIG_SYS_LATCH1_RESET
);
193 out_le16((void *)LATCH0_BASE
, CONFIG_SYS_LATCH0_BOOT
);
194 out_le16((void *)LATCH1_BASE
, CONFIG_SYS_LATCH1_BOOT
);
198 void gd405ep_setup_hw(void)
201 * set "startup-finished"-gpios
203 gpio_write_bit(21, 0);
204 gpio_write_bit(22, 1);
207 int gd405ep_get_fpga_done(unsigned fpga
)
209 return in_le16((void *)LATCH2_BASE
) & CONFIG_SYS_FPGA_DONE(fpga
);