board/gdsys/405ep/iocon.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <asm/ppc4xx-gpio.h>
  29
  30 #include "405ep.h"
  31 #include <gdsys_fpga.h>
  32
  33 #include "../common/osd.h"
  34
  35 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  36 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  37 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  38
  39 enum {
  40         UNITTYPE_MAIN_SERVER = 0,
  41         UNITTYPE_MAIN_USER = 1,
  42         UNITTYPE_VIDEO_SERVER = 2,
  43         UNITTYPE_VIDEO_USER = 3,
  44 };
  45
  46 enum {
  47         HWVER_100 = 0,
  48         HWVER_104 = 1,
  49         HWVER_110 = 2,
  50 };
  51
  52 enum {
  53         COMPRESSION_NONE = 0,
  54         COMPRESSION_TYPE1_DELTA,
  55 };
  56
  57 enum {
  58         AUDIO_NONE = 0,
  59         AUDIO_TX = 1,
  60         AUDIO_RX = 2,
  61         AUDIO_RXTX = 3,
  62 };
  63
  64 enum {
  65         SYSCLK_147456 = 0,
  66 };
  67
  68 enum {
  69         RAM_DDR2_32 = 0,
  70 };
  71
  72 /*
  73  * Check Board Identity:
  74  */
  75 int checkboard(void)
  76 {
  77         char *s = getenv("serial#");
  78
  79         puts("Board: ");
  80
  81         puts("IoCon");
  82
  83         if (s != NULL) {
  84                 puts(", serial# ");
  85                 puts(s);
  86         }
  87
  88         puts("\n");
  89
  90         return 0;
  91 }
  92
  93 static void print_fpga_info(void)
  94 {
  95         struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
  96         u16 versions = in_le16(&fpga->versions);
  97         u16 fpga_version = in_le16(&fpga->fpga_version);
  98         u16 fpga_features = in_le16(&fpga->fpga_features);
  99         unsigned unit_type;
 100         unsigned hardware_version;
 101         unsigned feature_compression;
 102         unsigned feature_osd;
 103         unsigned feature_audio;
 104         unsigned feature_sysclock;
 105         unsigned feature_ramconfig;
 106         unsigned feature_carriers;
 107         unsigned feature_video_channels;
 108
 109         unit_type = (versions & 0xf000) >> 12;
 110         hardware_version = versions & 0x000f;
 111         feature_compression = (fpga_features & 0xe000) >> 13;
 112         feature_osd = fpga_features & (1<<11);
 113         feature_audio = (fpga_features & 0x0600) >> 9;
 114         feature_sysclock = (fpga_features & 0x0180) >> 7;
 115         feature_ramconfig = (fpga_features & 0x0060) >> 5;
 116         feature_carriers = (fpga_features & 0x000c) >> 2;
 117         feature_video_channels = fpga_features & 0x0003;
 118
 119         switch (unit_type) {
 120         case UNITTYPE_MAIN_USER:
 121                 printf("Mainchannel");
 122                 break;
 123
 124         case UNITTYPE_VIDEO_USER:
 125                 printf("Videochannel");
 126                 break;
 127
 128         default:
 129                 printf("UnitType %d(not supported)", unit_type);
 130                 break;
 131         }
 132
 133         switch (hardware_version) {
 134         case HWVER_100:
 135                 printf(" HW-Ver 1.00\n");
 136                 break;
 137
 138         case HWVER_104:
 139                 printf(" HW-Ver 1.04\n");
 140                 break;
 141
 142         case HWVER_110:
 143                 printf(" HW-Ver 1.10\n");
 144                 break;
 145
 146         default:
 147                 printf(" HW-Ver %d(not supported)\n",
 148                        hardware_version);
 149                 break;
 150         }
 151
 152         printf("       FPGA V %d.%02d, features:",
 153                 fpga_version / 100, fpga_version % 100);
 154
 155
 156         switch (feature_compression) {
 157         case COMPRESSION_NONE:
 158                 printf(" no compression");
 159                 break;
 160
 161         case COMPRESSION_TYPE1_DELTA:
 162                 printf(" type1-deltacompression");
 163                 break;
 164
 165         default:
 166                 printf(" compression %d(not supported)", feature_compression);
 167                 break;
 168         }
 169
 170         printf(", %sosd", feature_osd ? "" : "no ");
 171
 172         switch (feature_audio) {
 173         case AUDIO_NONE:
 174                 printf(", no audio");
 175                 break;
 176
 177         case AUDIO_TX:
 178                 printf(", audio tx");
 179                 break;
 180
 181         case AUDIO_RX:
 182                 printf(", audio rx");
 183                 break;
 184
 185         case AUDIO_RXTX:
 186                 printf(", audio rx+tx");
 187                 break;
 188
 189         default:
 190                 printf(", audio %d(not supported)", feature_audio);
 191                 break;
 192         }
 193
 194         puts(",\n       ");
 195
 196         switch (feature_sysclock) {
 197         case SYSCLK_147456:
 198                 printf("clock 147.456 MHz");
 199                 break;
 200
 201         default:
 202                 printf("clock %d(not supported)", feature_sysclock);
 203                 break;
 204         }
 205
 206         switch (feature_ramconfig) {
 207         case RAM_DDR2_32:
 208                 printf(", RAM 32 bit DDR2");
 209                 break;
 210
 211         default:
 212                 printf(", RAM %d(not supported)", feature_ramconfig);
 213                 break;
 214         }
 215
 216         printf(", %d carrier(s)", feature_carriers);
 217
 218         printf(", %d video channel(s)\n", feature_video_channels);
 219 }
 220
 221 int last_stage_init(void)
 222 {
 223         print_fpga_info();
 224
 225         return osd_probe(0);
 226 }
 227
 228 /*
 229  * provide access to fpga gpios (for I2C bitbang)
 230  */
 231 void fpga_gpio_set(int pin)
 232 {
 233         out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
 234 }
 235
 236 void fpga_gpio_clear(int pin)
 237 {
 238         out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
 239 }
 240
 241 int fpga_gpio_get(int pin)
 242 {
 243         return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
 244 }
 245
 246 void gd405ep_init(void)
 247 {
 248 }
 249
 250 void gd405ep_set_fpga_reset(unsigned state)
 251 {
 252         if (state) {
 253                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 254                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 255         } else {
 256                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 257                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 258         }
 259 }
 260
 261 void gd405ep_setup_hw(void)
 262 {
 263         /*
 264          * set "startup-finished"-gpios
 265          */
 266         gpio_write_bit(21, 0);
 267         gpio_write_bit(22, 1);
 268 }
 269
 270 int gd405ep_get_fpga_done(unsigned fpga)
 271 {
 272         return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
 273 }