board/gdsys/405ep/neo.c

   1 /*
   2  * (C) Copyright 2011
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <asm/ppc4xx-gpio.h>
  13 #include <dtt.h>
  14
  15 #include "405ep.h"
  16 #include <gdsys_fpga.h>
  17
  18 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  19 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  20 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  21
  22 enum {
  23         UNITTYPE_CCX16 = 1,
  24         UNITTYPE_CCIP216 = 2,
  25 };
  26
  27 enum {
  28         HWVER_300 = 3,
  29 };
  30
  31 int misc_init_r(void)
  32 {
  33         /* startup fans */
  34         dtt_init();
  35
  36         return 0;
  37 }
  38
  39 int checkboard(void)
  40 {
  41         char *s = getenv("serial#");
  42
  43         puts("Board: CATCenter Neo");
  44
  45         if (s != NULL) {
  46                 puts(", serial# ");
  47                 puts(s);
  48         }
  49
  50         puts("\n");
  51
  52         return 0;
  53 }
  54
  55 static void print_fpga_info(void)
  56 {
  57         struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
  58         u16 versions = in_le16(&fpga->versions);
  59         u16 fpga_version = in_le16(&fpga->fpga_version);
  60         u16 fpga_features = in_le16(&fpga->fpga_features);
  61         int fpga_state = get_fpga_state(0);
  62         unsigned unit_type;
  63         unsigned hardware_version;
  64         unsigned feature_channels;
  65
  66         puts("FPGA:  ");
  67         if (fpga_state & FPGA_STATE_DONE_FAILED) {
  68                 printf(" done timed out\n");
  69                 return;
  70         }
  71
  72         if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
  73                 printf(" refelectione test failed\n");
  74                 return;
  75         }
  76
  77         unit_type = (versions & 0xf000) >> 12;
  78         hardware_version = versions & 0x000f;
  79         feature_channels = fpga_features & 0x007f;
  80
  81         switch (unit_type) {
  82         case UNITTYPE_CCX16:
  83                 printf("CCX-Switch");
  84                 break;
  85
  86         default:
  87                 printf("UnitType %d(not supported)", unit_type);
  88                 break;
  89         }
  90
  91         switch (hardware_version) {
  92         case HWVER_300:
  93                 printf(" HW-Ver 3.00-3.12\n");
  94                 break;
  95
  96         default:
  97                 printf(" HW-Ver %d(not supported)\n",
  98                        hardware_version);
  99                 break;
 100         }
 101
 102         printf("       FPGA V %d.%02d, features:",
 103                 fpga_version / 100, fpga_version % 100);
 104
 105         printf(" %d channel(s)\n", feature_channels);
 106 }
 107
 108 int last_stage_init(void)
 109 {
 110         print_fpga_info();
 111
 112         return 0;
 113 }
 114
 115 void gd405ep_init(void)
 116 {
 117 }
 118
 119 void gd405ep_set_fpga_reset(unsigned state)
 120 {
 121         if (state) {
 122                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 123                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 124         } else {
 125                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 126                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 127         }
 128 }
 129
 130 void gd405ep_setup_hw(void)
 131 {
 132         /*
 133          * set "startup-finished"-gpios
 134          */
 135         gpio_write_bit(21, 0);
 136         gpio_write_bit(22, 1);
 137 }
 138
 139 int gd405ep_get_fpga_done(unsigned fpga)
 140 {
 141         /*
 142          * Neo hardware has no FPGA-DONE GPIO
 143          */
 144         return 1;
 145 }