board/gdsys/common/dp501.c

   1 /*
   2  * (C) Copyright 2012
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <errno.h>
  13 #include <i2c.h>
  14
  15 static void dp501_setbits(u8 addr, u8 reg, u8 mask)
  16 {
  17         u8 val;
  18
  19         val = i2c_reg_read(addr, reg);
  20         setbits_8(&val, mask);
  21         i2c_reg_write(addr, reg, val);
  22 }
  23
  24 static void dp501_clrbits(u8 addr, u8 reg, u8 mask)
  25 {
  26         u8 val;
  27
  28         val = i2c_reg_read(addr, reg);
  29         clrbits_8(&val, mask);
  30         i2c_reg_write(addr, reg, val);
  31 }
  32
  33 static int dp501_detect_cable_adapter(u8 addr)
  34 {
  35         u8 val = i2c_reg_read(addr, 0x00);
  36
  37         return !(val & 0x04);
  38 }
  39
  40 static void dp501_link_training(u8 addr)
  41 {
  42         u8 val;
  43
  44         val = i2c_reg_read(addr, 0x51);
  45         i2c_reg_write(addr, 0x5d, val); /* set link_bw */
  46         val = i2c_reg_read(addr, 0x52);
  47         i2c_reg_write(addr, 0x5e, val); /* set lane_cnt */
  48         val = i2c_reg_read(addr, 0x53);
  49         i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */
  50
  51         i2c_reg_write(addr, 0x5f, 0x0d); /* start training */
  52 }
  53
  54 void dp501_powerup(u8 addr)
  55 {
  56         dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
  57         dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
  58         i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
  59         dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
  60         dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
  61         i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
  62         dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
  63         dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
  64         dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */
  65
  66 #ifdef CONFIG_SYS_DP501_VCAPCTRL0
  67         i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
  68 #else
  69         i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
  70 #endif
  71
  72 #ifdef CONFIG_SYS_DP501_DIFFERENTIAL
  73         i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
  74         i2c_reg_write(addr + 2, 0x25, 0x04);
  75         i2c_reg_write(addr + 2, 0x26, 0x10);
  76 #else
  77         i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
  78 #endif
  79
  80         i2c_reg_write(addr + 2, 0x1a, 0x04); /* SPDIF input method TTL */
  81
  82         i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
  83         i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
  84         i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
  85         i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
  86         i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
  87         i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
  88         dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
  89         i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
  90         i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
  91         i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
  92
  93         if (dp501_detect_cable_adapter(addr)) {
  94                 printf("DVI/HDMI cable adapter detected\n");
  95                 i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */
  96                 dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
  97         } else {
  98                 printf("no DVI/HDMI cable adapter detected\n");
  99                 dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
 100
 101                 dp501_link_training(addr);
 102         }
 103 }
 104
 105 void dp501_powerdown(u8 addr)
 106 {
 107         dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
 108 }