3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
14 #include <gdsys_fpga.h>
16 #define ICS8N3QV01_I2C_ADDR 0x6E
17 #define ICS8N3QV01_FREF 114285000
18 #define ICS8N3QV01_FREF_LL 114285000LL
19 #define ICS8N3QV01_F_DEFAULT_0 156250000LL
20 #define ICS8N3QV01_F_DEFAULT_1 125000000LL
21 #define ICS8N3QV01_F_DEFAULT_2 100000000LL
22 #define ICS8N3QV01_F_DEFAULT_3 25175000LL
24 #define SIL1178_MASTER_I2C_ADDRESS 0x38
25 #define SIL1178_SLAVE_I2C_ADDRESS 0x39
27 #define DP501_I2C_ADDR 0x08
29 #define PIXCLK_640_480_60 25180000
31 #ifdef CONFIG_SYS_OSD_DH
32 #define MAX_OSD_SCREEN 8
35 #define MAX_OSD_SCREEN 4
38 #ifdef CONFIG_SYS_OSD_DH
39 #define OSD_SET_REG(screen, fld, val) \
41 if (screen >= OSD_DH_BASE) \
42 FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
44 FPGA_SET_REG(screen, osd0.fld, val); \
47 #define OSD_SET_REG(screen, fld, val) \
48 FPGA_SET_REG(screen, osd0.fld, val)
51 #ifdef CONFIG_SYS_OSD_DH
52 #define OSD_GET_REG(screen, fld, val) \
54 if (screen >= OSD_DH_BASE) \
55 FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
57 FPGA_GET_REG(screen, osd0.fld, val); \
60 #define OSD_GET_REG(screen, fld, val) \
61 FPGA_GET_REG(screen, osd0.fld, val)
64 unsigned int base_width
;
65 unsigned int base_height
;
69 unsigned int osd_screen_mask
= 0;
71 #ifdef CONFIG_SYS_ICS8N3QV01_I2C
72 int ics8n3qv01_i2c
[] = CONFIG_SYS_ICS8N3QV01_I2C
;
75 #ifdef CONFIG_SYS_SIL1178_I2C
76 int sil1178_i2c
[] = CONFIG_SYS_SIL1178_I2C
;
79 #ifdef CONFIG_SYS_DP501_I2C
80 int dp501_i2c
[] = CONFIG_SYS_DP501_I2C
;
83 #ifdef CONFIG_SYS_DP501_BASE
84 int dp501_base
[] = CONFIG_SYS_DP501_BASE
;
87 #ifdef CONFIG_SYS_MPC92469AC
88 static void mpc92469ac_calc_parameters(unsigned int fout
,
89 unsigned int *post_div
, unsigned int *feedback_div
)
91 unsigned int n
= *post_div
;
92 unsigned int m
= *feedback_div
;
94 unsigned int b
= 14745600 / 16;
98 else if (fout
< 100339199)
100 else if (fout
< 200678399)
105 a
= fout
* n
+ (b
/ 2); /* add b/2 for proper rounding */
113 static void mpc92469ac_set(unsigned screen
, unsigned int fout
)
117 unsigned int bitval
= 0;
118 mpc92469ac_calc_parameters(fout
, &n
, &m
);
135 FPGA_SET_REG(screen
, mpc3w_control
, (bitval
<< 9) | m
);
139 #ifdef CONFIG_SYS_ICS8N3QV01_I2C
141 static unsigned int ics8n3qv01_get_fout_calc(unsigned index
)
143 unsigned long long n
;
144 unsigned long long mint
;
145 unsigned long long mfrac
;
146 u8 reg_a
, reg_b
, reg_c
, reg_d
, reg_f
;
147 unsigned long long fout_calc
;
152 reg_a
= i2c_reg_read(ICS8N3QV01_I2C_ADDR
, 0 + index
);
153 reg_b
= i2c_reg_read(ICS8N3QV01_I2C_ADDR
, 4 + index
);
154 reg_c
= i2c_reg_read(ICS8N3QV01_I2C_ADDR
, 8 + index
);
155 reg_d
= i2c_reg_read(ICS8N3QV01_I2C_ADDR
, 12 + index
);
156 reg_f
= i2c_reg_read(ICS8N3QV01_I2C_ADDR
, 20 + index
);
158 mint
= ((reg_a
>> 1) & 0x1f) | (reg_f
& 0x20);
159 mfrac
= ((reg_a
& 0x01) << 17) | (reg_b
<< 9) | (reg_c
<< 1)
163 fout_calc
= (mint
* ICS8N3QV01_FREF_LL
164 + mfrac
* ICS8N3QV01_FREF_LL
/ 262144LL
165 + ICS8N3QV01_FREF_LL
/ 524288LL
175 static void ics8n3qv01_calc_parameters(unsigned int fout
,
176 unsigned int *_mint
, unsigned int *_mfrac
,
180 unsigned int foutiic
;
181 unsigned int fvcoiic
;
183 unsigned long long mfrac
;
185 n
= (2215000000U + fout
/ 2) / fout
;
186 if ((n
& 1) && (n
> 5))
189 foutiic
= fout
- (fout
/ 10000);
190 fvcoiic
= foutiic
* n
;
192 mint
= fvcoiic
/ 114285000;
193 if ((mint
< 17) || (mint
> 63))
194 printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
196 mfrac
= ((unsigned long long)fvcoiic
% 114285000LL) * 262144LL
204 static void ics8n3qv01_set(unsigned int fout
)
209 unsigned int fout_calc
;
210 unsigned long long fout_prog
;
212 u8 reg0
, reg4
, reg8
, reg12
, reg18
, reg20
;
214 fout_calc
= ics8n3qv01_get_fout_calc(1);
215 off_ppm
= (fout_calc
- ICS8N3QV01_F_DEFAULT_1
) * 1000000
216 / ICS8N3QV01_F_DEFAULT_1
;
217 printf(" PLL is off by %lld ppm\n", off_ppm
);
218 fout_prog
= (unsigned long long)fout
* (unsigned long long)fout_calc
219 / ICS8N3QV01_F_DEFAULT_1
;
220 ics8n3qv01_calc_parameters(fout_prog
, &mint
, &mfrac
, &n
);
222 reg0
= i2c_reg_read(ICS8N3QV01_I2C_ADDR
, 0) & 0xc0;
223 reg0
|= (mint
& 0x1f) << 1;
224 reg0
|= (mfrac
>> 17) & 0x01;
225 i2c_reg_write(ICS8N3QV01_I2C_ADDR
, 0, reg0
);
228 i2c_reg_write(ICS8N3QV01_I2C_ADDR
, 4, reg4
);
231 i2c_reg_write(ICS8N3QV01_I2C_ADDR
, 8, reg8
);
235 i2c_reg_write(ICS8N3QV01_I2C_ADDR
, 12, reg12
);
237 reg18
= i2c_reg_read(ICS8N3QV01_I2C_ADDR
, 18) & 0x03;
239 i2c_reg_write(ICS8N3QV01_I2C_ADDR
, 18, reg18
);
241 reg20
= i2c_reg_read(ICS8N3QV01_I2C_ADDR
, 20) & 0x1f;
242 reg20
|= mint
& (1 << 5);
243 i2c_reg_write(ICS8N3QV01_I2C_ADDR
, 20, reg20
);
247 static int osd_write_videomem(unsigned screen
, unsigned offset
,
248 u16
*data
, size_t charcount
)
252 for (k
= 0; k
< charcount
; ++k
) {
253 if (offset
+ k
>= bufsize
)
255 #ifdef CONFIG_SYS_OSD_DH
256 if (screen
>= OSD_DH_BASE
)
257 FPGA_SET_REG(screen
- OSD_DH_BASE
,
258 videomem1
[offset
+ k
], data
[k
]);
260 FPGA_SET_REG(screen
, videomem0
[offset
+ k
], data
[k
]);
262 FPGA_SET_REG(screen
, videomem0
[offset
+ k
], data
[k
]);
269 static int osd_print(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
278 for (screen
= 0; screen
< MAX_OSD_SCREEN
; ++screen
) {
288 if (!(osd_screen_mask
& (1 << screen
)))
291 x
= simple_strtoul(argv
[1], NULL
, 16);
292 y
= simple_strtoul(argv
[2], NULL
, 16);
293 color
= simple_strtoul(argv
[3], NULL
, 16);
295 charcount
= strlen(text
);
296 len
= (charcount
> bufsize
) ? bufsize
: charcount
;
298 for (k
= 0; k
< len
; ++k
)
299 buf
[k
] = (text
[k
] << 8) | color
;
301 res
= osd_write_videomem(screen
, y
* base_width
+ x
, buf
, len
);
309 int osd_probe(unsigned screen
)
313 int old_bus
= i2c_get_bus_num();
314 bool pixclock_present
= false;
315 bool output_driver_present
= false;
316 #ifdef CONFIG_SYS_DP501_I2C
317 #ifdef CONFIG_SYS_DP501_BASE
318 uint8_t dp501_addr
= dp501_base
[screen
];
320 uint8_t dp501_addr
= DP501_I2C_ADDR
;
324 OSD_GET_REG(0, version
, &version
);
325 OSD_GET_REG(0, features
, &features
);
327 base_width
= ((features
& 0x3f00) >> 8) + 1;
328 base_height
= (features
& 0x001f) + 1;
329 bufsize
= base_width
* base_height
;
330 buf
= malloc(sizeof(u16
) * bufsize
);
334 #ifdef CONFIG_SYS_OSD_DH
335 printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
336 (screen
>= OSD_DH_BASE
) ? (screen
- OSD_DH_BASE
) : screen
,
337 (screen
> 3) ? 1 : 0, version
/100, version
%100, base_width
,
340 printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
341 screen
, version
/100, version
%100, base_width
, base_height
);
345 #ifdef CONFIG_SYS_MPC92469AC
346 pixclock_present
= true;
347 mpc92469ac_set(screen
, PIXCLK_640_480_60
);
350 #ifdef CONFIG_SYS_ICS8N3QV01_I2C
351 i2c_set_bus_num(ics8n3qv01_i2c
[screen
]);
352 if (!i2c_probe(ICS8N3QV01_I2C_ADDR
)) {
353 ics8n3qv01_set(PIXCLK_640_480_60
);
354 pixclock_present
= true;
358 if (!pixclock_present
)
359 printf(" no pixelclock found\n");
361 /* setup output driver */
363 #ifdef CONFIG_SYS_CH7301_I2C
364 if (!ch7301_probe(screen
, true))
365 output_driver_present
= true;
368 #ifdef CONFIG_SYS_SIL1178_I2C
369 i2c_set_bus_num(sil1178_i2c
[screen
]);
370 if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS
)) {
371 if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS
, 0x02) == 0x06) {
373 * magic initialization sequence,
374 * adapted from datasheet
376 i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS
, 0x08, 0x36);
377 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS
, 0x0f, 0x44);
378 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS
, 0x0f, 0x4c);
379 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS
, 0x0e, 0x10);
380 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS
, 0x0a, 0x80);
381 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS
, 0x09, 0x30);
382 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS
, 0x0c, 0x89);
383 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS
, 0x0d, 0x60);
384 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS
, 0x08, 0x36);
385 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS
, 0x08, 0x37);
386 output_driver_present
= true;
391 #ifdef CONFIG_SYS_DP501_I2C
392 i2c_set_bus_num(dp501_i2c
[screen
]);
393 if (!i2c_probe(dp501_addr
)) {
394 dp501_powerup(dp501_addr
);
395 output_driver_present
= true;
399 if (!output_driver_present
)
400 printf(" no output driver found\n");
402 OSD_SET_REG(screen
, control
, 0x0049);
404 OSD_SET_REG(screen
, xy_size
, ((32 - 1) << 8) | (16 - 1));
405 OSD_SET_REG(screen
, x_pos
, 0x007f);
406 OSD_SET_REG(screen
, y_pos
, 0x005f);
408 if (pixclock_present
&& output_driver_present
)
409 osd_screen_mask
|= 1 << screen
;
411 i2c_set_bus_num(old_bus
);
416 int osd_write(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
420 if ((argc
< 4) || (strlen(argv
[3]) % 4)) {
425 for (screen
= 0; screen
< MAX_OSD_SCREEN
; ++screen
) {
429 u16 buffer
[base_width
];
432 unsigned count
= (argc
> 4) ?
433 simple_strtoul(argv
[4], NULL
, 16) : 1;
435 if (!(osd_screen_mask
& (1 << screen
)))
438 x
= simple_strtoul(argv
[1], NULL
, 16);
439 y
= simple_strtoul(argv
[2], NULL
, 16);
446 memcpy(substr
, rp
, 4);
448 *wp
= simple_strtoul(substr
, NULL
, 16);
452 if (wp
- buffer
> base_width
)
456 for (k
= 0; k
< count
; ++k
) {
458 y
* base_width
+ x
+ k
* (wp
- buffer
);
459 osd_write_videomem(screen
, offset
, buffer
,
468 osdw
, 5, 0, osd_write
,
469 "write 16-bit hex encoded buffer to osd memory",
470 "pos_x pos_y buffer count\n"
474 osdp
, 5, 0, osd_print
,
475 "write ASCII buffer to osd memory",
476 "pos_x pos_y color text\n"