board/gdsys/gdppc440etx/gdppc440etx.c

   1 /*
   2  * (C) Copyright 2008
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * Based on board/amcc/yosemite/yosemite.c
   6  * (C) Copyright 2006-2007
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/ppc4xx.h>
  14 #include <asm/processor.h>
  15 #include <asm/io.h>
  16 #include <asm/4xx_pci.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 /* info for FLASH chips */
  21 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  22
  23 int board_early_init_f(void)
  24 {
  25         register uint reg;
  26
  27         /*
  28          * Setup the external bus controller/chip selects
  29          */
  30         mfebc(EBC0_CFG, reg);
  31         mtebc(EBC0_CFG, reg | 0x04000000);              /* Set ATC */
  32
  33         /*
  34          * Setup the GPIO pins
  35          */
  36
  37         /* setup Address lines for flash size 64Meg. */
  38         out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
  39         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
  40         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
  41
  42         /* setup emac */
  43         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  44         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  45         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  46         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  47         out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  48
  49         /* UART0 and UART1*/
  50         out32(GPIO1_TCR, in32(GPIO1_TCR)     | 0x16000000);
  51         out32(GPIO1_OSRL, in32(GPIO1_OSRL)   | 0x02180000);
  52         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
  53         out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
  54
  55         /* disable boot-eeprom WP */
  56         out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
  57         out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
  58         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
  59         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
  60         out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
  61
  62         /* external interrupts IRQ0...3 */
  63         out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
  64         out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
  65         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  66
  67
  68         /*
  69          * Setup the interrupt controller polarities, triggers, etc.
  70          */
  71         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  72         mtdcr(UIC0ER, 0x00000000);      /* disable all */
  73         mtdcr(UIC0CR, 0x00000009);      /* ATI & UIC1 crit are critical */
  74         mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
  75         mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
  76         mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
  77         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  78
  79         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  80         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  81         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  82         mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
  83         mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
  84         mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
  85         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  86
  87         /*
  88          * Setup other serial configuration
  89          */
  90         mfsdr(SDR0_PCI0, reg);
  91         mtsdr(SDR0_PCI0, 0x80000000 | reg);     /* PCI arbiter enabled */
  92         mtsdr(SDR0_PFC0, 0x00003e00);   /* Pin function */
  93         mtsdr(SDR0_PFC1, 0x00048000);   /* Pin function: UART0 has 4 pins */
  94
  95         return 0;
  96 }
  97
  98 int misc_init_r(void)
  99 {
 100         uint pbcr;
 101         int size_val;
 102         uint sz;
 103
 104         /* Re-do sizing to get full correct info */
 105         mfebc(PB0CR, pbcr);
 106
 107         if (gd->bd->bi_flashsize > 0x08000000)
 108                 panic("Max. flash banksize is 128 MB!\n");
 109
 110         for (sz = gd->bd->bi_flashsize, size_val = 7;
 111             ((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
 112                 sz <<= 1;
 113
 114         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 115         mtebc(PB0CR, pbcr);
 116
 117         /* adjust flash start and offset */
 118         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 119         gd->bd->bi_flashoffset = 0;
 120
 121         /* Monitor protection ON by default */
 122         (void)flash_protect(FLAG_PROTECT_SET,
 123                             -CONFIG_SYS_MONITOR_LEN,
 124                             0xffffffff,
 125                             &flash_info[0]);
 126
 127         return 0;
 128 }
 129
 130 int checkboard(void)
 131 {
 132         char buf[64];
 133         int i = getenv_f("serial#", buf, sizeof(buf));
 134
 135         printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
 136
 137         if (i > 0) {
 138                 puts(", serial# ");
 139                 puts(buf);
 140         }
 141         putc('\n');
 142
 143         return 0;
 144 }
 145
 146 /*
 147  * Override weak pci_pre_init()
 148  */
 149 #if defined(CONFIG_PCI)
 150 int pci_pre_init(struct pci_controller *hose)
 151 {
 152         /* First call common code */
 153         __pci_pre_init(hose);
 154
 155         /* enable 66 MHz ext. Clock */
 156         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
 157         out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
 158
 159         return 1;
 160 }
 161 #endif  /* defined(CONFIG_PCI) */