board/gdsys/intip/intip.c

   1 /*
   2  * (C) Copyright 2009
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * Based on board/amcc/canyonlands/canyonlands.c
   6  * (C) Copyright 2008
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <ppc440.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <i2c.h>
  30 #include <asm/processor.h>
  31 #include <asm/io.h>
  32 #include <asm/mmu.h>
  33 #include <asm/4xx_pcie.h>
  34 #include <asm/gpio.h>
  35
  36 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define CONFIG_SYS_BCSR3_PCIE           0x10
  41
  42 int board_early_init_f(void)
  43 {
  44         /*
  45          * Setup the interrupt controller polarities, triggers, etc.
  46          */
  47         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  48         mtdcr(uic0er, 0x00000000);      /* disable all */
  49         mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
  50         mtdcr(uic0pr, 0xffffffff);      /* per ref-board manual */
  51         mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
  52         mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
  53         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  54
  55         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  56         mtdcr(uic1er, 0x00000000);      /* disable all */
  57         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  58         mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
  59         mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
  60         mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
  61         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  62
  63         mtdcr(uic2sr, 0xffffffff);      /* clear all */
  64         mtdcr(uic2er, 0x00000000);      /* disable all */
  65         mtdcr(uic2cr, 0x00000000);      /* all non-critical */
  66         mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
  67         mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
  68         mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
  69         mtdcr(uic2sr, 0xffffffff);      /* clear all */
  70
  71         mtdcr(uic3sr, 0xffffffff);      /* clear all */
  72         mtdcr(uic3er, 0x00000000);      /* disable all */
  73         mtdcr(uic3cr, 0x00000000);      /* all non-critical */
  74         mtdcr(uic3pr, 0xffffffff);      /* per ref-board manual */
  75         mtdcr(uic3tr, 0x00000000);      /* per ref-board manual */
  76         mtdcr(uic3vr, 0x00000000);      /* int31 highest, base=0x000 */
  77         mtdcr(uic3sr, 0xffffffff);      /* clear all */
  78
  79         /*
  80          * Configure PFC (Pin Function Control) registers
  81          * enable GPIO 49-63
  82          * UART0: 4 pins
  83          */
  84         mtsdr(SDR0_PFC0, 0x00007fff);
  85         mtsdr(SDR0_PFC1, 0x00040000);
  86
  87         /* Enable PCI host functionality in SDR0_PCI0 */
  88         mtsdr(SDR0_PCI0, 0xe0000000);
  89
  90         mtsdr(SDR0_SRST1, 0);   /* Pull AHB out of reset default=1 */
  91
  92         /* Setup PLB4-AHB bridge based on the system address map */
  93         mtdcr(AHB_TOP, 0x8000004B);
  94         mtdcr(AHB_BOT, 0x8000004B);
  95
  96         /*
  97         * Configure USB-STP pins as alternate and not GPIO
  98         * It seems to be neccessary to configure the STP pins as GPIO
  99         * input at powerup (perhaps while USB reset is asserted). So
 100         * we configure those pins to their "real" function now.
 101         */
 102         gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 103         gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 104
 105         /* Trigger board component reset */
 106         out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
 107         out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
 108         udelay(50);
 109         out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
 110         out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
 111         udelay(50);
 112         out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
 113         out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
 114
 115         return 0;
 116 }
 117
 118 int get_cpu_num(void)
 119 {
 120         int cpu = NA_OR_UNKNOWN_CPU;
 121
 122         return cpu;
 123 }
 124
 125 int checkboard(void)
 126 {
 127         char *s = getenv("serial#");
 128
 129 #ifdef CONFIG_DEVCONCENTER
 130         printf("Board: DevCon-Center");
 131 #else
 132         printf("Board: Intip");
 133 #endif
 134
 135         if (s != NULL) {
 136                 puts(", serial# ");
 137                 puts(s);
 138         }
 139         putc('\n');
 140
 141         return 0;
 142 }
 143
 144 /*
 145  *  pci_target_init
 146  *
 147  *      The bootstrap configuration provides default settings for the pci
 148  *      inbound map (PIM). But the bootstrap config choices are limited and
 149  *      may not be sufficient for a given board.
 150  */
 151 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 152 void pci_target_init(struct pci_controller *hose)
 153 {
 154         /*
 155          * Disable everything
 156          */
 157         out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
 158         out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
 159         out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
 160         out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
 161
 162         /*
 163          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 164          * strapping options to not support sizes such as 128/256 MB.
 165          */
 166         out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
 167         out_le32((void *)PCIX0_PIM0LAH, 0);
 168         out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 169         out_le32((void *)PCIX0_BAR0, 0);
 170
 171         /*
 172          * Program the board's subsystem id/vendor id
 173          */
 174         out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
 175         out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 176
 177         out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
 178 }
 179 #endif  /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 180
 181 #if defined(CONFIG_PCI)
 182 /*
 183  * is_pci_host
 184  *
 185  * This routine is called to determine if a pci scan should be
 186  * performed. With various hardware environments (especially cPCI and
 187  * PPMC) it's insufficient to depend on the state of the arbiter enable
 188  * bit in the strap register, or generic host/adapter assumptions.
 189  *
 190  * Rather than hard-code a bad assumption in the general 440 code, the
 191  * 440 pci code requires the board to decide at runtime.
 192  *
 193  * Return 0 for adapter mode, non-zero for host (monarch) mode.
 194  */
 195 int is_pci_host(struct pci_controller *hose)
 196 {
 197         /* Board is always configured as host. */
 198         return 1;
 199 }
 200 #endif /* CONFIG_PCI */
 201
 202 int board_early_init_r(void)
 203 {
 204         /*
 205          * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
 206          * (Spansion 29GL512), but the boot EBC mapping only supports a maximum
 207          * of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
 208          * To solve this problem, the FLASH has to get remapped to another
 209          * EBC address which accepts bigger regions:
 210          *
 211          * 0xfn00.0000 -> 4.cn00.0000
 212          */
 213
 214         u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?
 215                 EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
 216
 217         /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
 218         mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L
 219                 | bxcr_bw
 220                 | EBC_BXCR_BU_RW
 221                 | EBC_BXCR_BW_16BIT);
 222
 223         /* Remove TLB entry of boot EBC mapping */
 224         remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
 225
 226         /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
 227         program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
 228                         CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
 229
 230         /*
 231          * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
 232          * 0xfc00.0000 is possible
 233          */
 234
 235         /*
 236          * Clear potential errors resulting from auto-calibration.
 237          * If not done, then we could get an interrupt later on when
 238          * exceptions are enabled.
 239          */
 240         set_mcsr(get_mcsr());
 241
 242         return 0;
 243 }
 244
 245 int misc_init_r(void)
 246 {
 247         u32 sdr0_srst1 = 0;
 248         u32 eth_cfg;
 249
 250         /*
 251          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 252          * This is board specific, so let's do it here.
 253          */
 254         mfsdr(SDR0_ETH_CFG, eth_cfg);
 255         /* disable SGMII mode */
 256         eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
 257                      SDR0_ETH_CFG_SGMII1_ENABLE |
 258                      SDR0_ETH_CFG_SGMII0_ENABLE);
 259         /* Set the for 2 RGMII mode */
 260         /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
 261         eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
 262         eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 263         mtsdr(SDR0_ETH_CFG, eth_cfg);
 264
 265         /*
 266          * The AHB Bridge core is held in reset after power-on or reset
 267          * so enable it now
 268          */
 269         mfsdr(SDR0_SRST1, sdr0_srst1);
 270         sdr0_srst1 &= ~SDR0_SRST1_AHB;
 271         mtsdr(SDR0_SRST1, sdr0_srst1);
 272
 273         return 0;
 274 }
 275
 276 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 277 extern void __ft_board_setup(void *blob, bd_t *bd);
 278
 279 void ft_board_setup(void *blob, bd_t *bd)
 280 {
 281         __ft_board_setup(blob, bd);
 282
 283         fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
 284                              "disabled", sizeof("disabled"), 1);
 285
 286         fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
 287                              "disabled", sizeof("disabled"), 1);
 288 }
 289 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */