board/gdsys/mpc8308/hrcon.c

   1 /*
   2  * (C) Copyright 2014
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <hwconfig.h>
  10 #include <i2c.h>
  11 #include <spi.h>
  12 #include <libfdt.h>
  13 #include <fdt_support.h>
  14 #include <pci.h>
  15 #include <mpc83xx.h>
  16 #include <fsl_esdhc.h>
  17 #include <asm/io.h>
  18 #include <asm/fsl_serdes.h>
  19 #include <asm/fsl_mpc83xx_serdes.h>
  20
  21 #include "mpc8308.h"
  22
  23 #include <gdsys_fpga.h>
  24
  25 #include "../common/ioep-fpga.h"
  26 #include "../common/osd.h"
  27 #include "../common/mclink.h"
  28 #include "../common/phy.h"
  29
  30 #include <pca953x.h>
  31 #include <pca9698.h>
  32
  33 #include <miiphy.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define MAX_MUX_CHANNELS 2
  38
  39 enum {
  40         MCFPGA_DONE = 1 << 0,
  41         MCFPGA_INIT_N = 1 << 1,
  42         MCFPGA_PROGRAM_N = 1 << 2,
  43         MCFPGA_UPDATE_ENABLE_N = 1 << 3,
  44         MCFPGA_RESET_N = 1 << 4,
  45 };
  46
  47 enum {
  48         GPIO_MDC = 1 << 14,
  49         GPIO_MDIO = 1 << 15,
  50 };
  51
  52 unsigned int mclink_fpgacount;
  53 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  54
  55 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
  56 {
  57         int res;
  58
  59         switch (fpga) {
  60         case 0:
  61                 out_le16(reg, data);
  62                 break;
  63         default:
  64                 res = mclink_send(fpga - 1, regoff, data);
  65                 if (res < 0) {
  66                         printf("mclink_send reg %02lx data %04x returned %d\n",
  67                                regoff, data, res);
  68                         return res;
  69                 }
  70                 break;
  71         }
  72
  73         return 0;
  74 }
  75
  76 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
  77 {
  78         int res;
  79
  80         switch (fpga) {
  81         case 0:
  82                 *data = in_le16(reg);
  83                 break;
  84         default:
  85                 if (fpga > mclink_fpgacount)
  86                         return -EINVAL;
  87                 res = mclink_receive(fpga - 1, regoff, data);
  88                 if (res < 0) {
  89                         printf("mclink_receive reg %02lx returned %d\n",
  90                                regoff, res);
  91                         return res;
  92                 }
  93         }
  94
  95         return 0;
  96 }
  97
  98 int checkboard(void)
  99 {
 100         char *s = getenv("serial#");
 101         bool hw_type_cat = pca9698_get_value(0x20, 20);
 102
 103         puts("Board: ");
 104
 105         printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
 106
 107         if (s != NULL) {
 108                 puts(", serial# ");
 109                 puts(s);
 110         }
 111
 112         puts("\n");
 113
 114         return 0;
 115 }
 116
 117 int last_stage_init(void)
 118 {
 119         int slaves;
 120         unsigned int k;
 121         unsigned int mux_ch;
 122         unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
 123         u16 fpga_features;
 124         bool hw_type_cat = pca9698_get_value(0x20, 20);
 125         bool ch0_rgmii2_present = false;
 126
 127         FPGA_GET_REG(0, fpga_features, &fpga_features);
 128
 129         /* Turn on Parade DP501 */
 130         pca9698_direction_output(0x20, 10, 1);
 131
 132         ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
 133
 134         /* wait for FPGA done, then reset FPGA */
 135         for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
 136                 unsigned int ctr = 0;
 137
 138                 if (i2c_probe(mclink_controllers[k]))
 139                         continue;
 140
 141                 while (!(pca953x_get_val(mclink_controllers[k])
 142                        & MCFPGA_DONE)) {
 143                         udelay(100000);
 144                         if (ctr++ > 5) {
 145                                 printf("no done for mclink_controller %d\n", k);
 146                                 break;
 147                         }
 148                 }
 149
 150                 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
 151                 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
 152                 udelay(10);
 153                 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
 154                                 MCFPGA_RESET_N);
 155         }
 156
 157         if (hw_type_cat) {
 158                 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
 159                                 bb_miiphy_write);
 160                 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
 161                         if ((mux_ch == 1) && !ch0_rgmii2_present)
 162                                 continue;
 163
 164                         setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
 165                 }
 166         }
 167
 168         /* give slave-PLLs and Parade DP501 some time to be up and running */
 169         udelay(500000);
 170
 171         mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
 172         slaves = mclink_probe();
 173         mclink_fpgacount = 0;
 174
 175         ioep_fpga_print_info(0);
 176         osd_probe(0);
 177
 178         if (slaves <= 0)
 179                 return 0;
 180
 181         mclink_fpgacount = slaves;
 182
 183         for (k = 1; k <= slaves; ++k) {
 184                 FPGA_GET_REG(k, fpga_features, &fpga_features);
 185
 186                 ioep_fpga_print_info(k);
 187                 osd_probe(k);
 188                 if (hw_type_cat) {
 189                         miiphy_register(bb_miiphy_buses[k].name,
 190                                         bb_miiphy_read, bb_miiphy_write);
 191                         setup_88e1514(bb_miiphy_buses[k].name, 0);
 192                 }
 193         }
 194
 195         return 0;
 196 }
 197
 198 /*
 199  * provide access to fpga gpios (for I2C bitbang)
 200  * (these may look all too simple but make iocon.h much more readable)
 201  */
 202 void fpga_gpio_set(unsigned int bus, int pin)
 203 {
 204         FPGA_SET_REG(bus, gpio.set, pin);
 205 }
 206
 207 void fpga_gpio_clear(unsigned int bus, int pin)
 208 {
 209         FPGA_SET_REG(bus, gpio.clear, pin);
 210 }
 211
 212 int fpga_gpio_get(unsigned int bus, int pin)
 213 {
 214         u16 val;
 215
 216         FPGA_GET_REG(bus, gpio.read, &val);
 217
 218         return val & pin;
 219 }
 220
 221 void mpc8308_init(void)
 222 {
 223         pca9698_direction_output(0x20, 4, 1);
 224 }
 225
 226 void mpc8308_set_fpga_reset(unsigned state)
 227 {
 228         pca9698_set_value(0x20, 4, state ? 0 : 1);
 229 }
 230
 231 void mpc8308_setup_hw(void)
 232 {
 233         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 234
 235         /*
 236          * set "startup-finished"-gpios
 237          */
 238         setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
 239         setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
 240 }
 241
 242 int mpc8308_get_fpga_done(unsigned fpga)
 243 {
 244         return pca9698_get_value(0x20, 19);
 245 }
 246
 247 #ifdef CONFIG_FSL_ESDHC
 248 int board_mmc_init(bd_t *bd)
 249 {
 250         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 251         sysconf83xx_t *sysconf = &immr->sysconf;
 252
 253         /* Enable cache snooping in eSDHC system configuration register */
 254         out_be32(&sysconf->sdhccr, 0x02000000);
 255
 256         return fsl_esdhc_mmc_init(bd);
 257 }
 258 #endif
 259
 260 static struct pci_region pcie_regions_0[] = {
 261         {
 262                 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
 263                 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
 264                 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
 265                 .flags = PCI_REGION_MEM,
 266         },
 267         {
 268                 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
 269                 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
 270                 .size = CONFIG_SYS_PCIE1_IO_SIZE,
 271                 .flags = PCI_REGION_IO,
 272         },
 273 };
 274
 275 void pci_init_board(void)
 276 {
 277         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 278         sysconf83xx_t *sysconf = &immr->sysconf;
 279         law83xx_t *pcie_law = sysconf->pcielaw;
 280         struct pci_region *pcie_reg[] = { pcie_regions_0 };
 281
 282         fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
 283                          FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 284
 285         /* Deassert the resets in the control register */
 286         out_be32(&sysconf->pecr1, 0xE0008000);
 287         udelay(2000);
 288
 289         /* Configure PCI Express Local Access Windows */
 290         out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
 291         out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
 292
 293         mpc83xx_pcie_init(1, pcie_reg);
 294 }
 295
 296 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 297 {
 298         info->portwidth = FLASH_CFI_16BIT;
 299         info->chipwidth = FLASH_CFI_BY16;
 300         info->interface = FLASH_CFI_X16;
 301         return 1;
 302 }
 303
 304 #if defined(CONFIG_OF_BOARD_SETUP)
 305 int ft_board_setup(void *blob, bd_t *bd)
 306 {
 307         ft_cpu_setup(blob, bd);
 308         fdt_fixup_dr_usb(blob, bd);
 309         fdt_fixup_esdhc(blob, bd);
 310
 311         return 0;
 312 }
 313 #endif
 314
 315 /*
 316  * FPGA MII bitbang implementation
 317  */
 318
 319 struct fpga_mii {
 320         unsigned fpga;
 321         int mdio;
 322 } fpga_mii[] = {
 323         { 0, 1},
 324         { 1, 1},
 325         { 2, 1},
 326         { 3, 1},
 327 };
 328
 329 static int mii_dummy_init(struct bb_miiphy_bus *bus)
 330 {
 331         return 0;
 332 }
 333
 334 static int mii_mdio_active(struct bb_miiphy_bus *bus)
 335 {
 336         struct fpga_mii *fpga_mii = bus->priv;
 337
 338         if (fpga_mii->mdio)
 339                 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
 340         else
 341                 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
 342
 343         return 0;
 344 }
 345
 346 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
 347 {
 348         struct fpga_mii *fpga_mii = bus->priv;
 349
 350         FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
 351
 352         return 0;
 353 }
 354
 355 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
 356 {
 357         struct fpga_mii *fpga_mii = bus->priv;
 358
 359         if (v)
 360                 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
 361         else
 362                 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
 363
 364         fpga_mii->mdio = v;
 365
 366         return 0;
 367 }
 368
 369 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
 370 {
 371         u16 gpio;
 372         struct fpga_mii *fpga_mii = bus->priv;
 373
 374         FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
 375
 376         *v = ((gpio & GPIO_MDIO) != 0);
 377
 378         return 0;
 379 }
 380
 381 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
 382 {
 383         struct fpga_mii *fpga_mii = bus->priv;
 384
 385         if (v)
 386                 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
 387         else
 388                 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
 389
 390         return 0;
 391 }
 392
 393 static int mii_delay(struct bb_miiphy_bus *bus)
 394 {
 395         udelay(1);
 396
 397         return 0;
 398 }
 399
 400 struct bb_miiphy_bus bb_miiphy_buses[] = {
 401         {
 402                 .name = "board0",
 403                 .init = mii_dummy_init,
 404                 .mdio_active = mii_mdio_active,
 405                 .mdio_tristate = mii_mdio_tristate,
 406                 .set_mdio = mii_set_mdio,
 407                 .get_mdio = mii_get_mdio,
 408                 .set_mdc = mii_set_mdc,
 409                 .delay = mii_delay,
 410                 .priv = &fpga_mii[0],
 411         },
 412         {
 413                 .name = "board1",
 414                 .init = mii_dummy_init,
 415                 .mdio_active = mii_mdio_active,
 416                 .mdio_tristate = mii_mdio_tristate,
 417                 .set_mdio = mii_set_mdio,
 418                 .get_mdio = mii_get_mdio,
 419                 .set_mdc = mii_set_mdc,
 420                 .delay = mii_delay,
 421                 .priv = &fpga_mii[1],
 422         },
 423         {
 424                 .name = "board2",
 425                 .init = mii_dummy_init,
 426                 .mdio_active = mii_mdio_active,
 427                 .mdio_tristate = mii_mdio_tristate,
 428                 .set_mdio = mii_set_mdio,
 429                 .get_mdio = mii_get_mdio,
 430                 .set_mdc = mii_set_mdc,
 431                 .delay = mii_delay,
 432                 .priv = &fpga_mii[2],
 433         },
 434         {
 435                 .name = "board3",
 436                 .init = mii_dummy_init,
 437                 .mdio_active = mii_mdio_active,
 438                 .mdio_tristate = mii_mdio_tristate,
 439                 .set_mdio = mii_set_mdio,
 440                 .get_mdio = mii_get_mdio,
 441                 .set_mdc = mii_set_mdc,
 442                 .delay = mii_delay,
 443                 .priv = &fpga_mii[3],
 444         },
 445 };
 446
 447 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
 448                           sizeof(bb_miiphy_buses[0]);