board/gdsys/mpc8308/mpc8308.c

   1 /*
   2  * (C) Copyright 2014
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <asm/global_data.h>
  13
  14 #include "mpc8308.h"
  15 #include <gdsys_fpga.h>
  16
  17 #define REFLECTION_TESTPATTERN 0xdede
  18 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  19
  20 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
  21 #define REFLECTION_TESTREG reflection_low
  22 #else
  23 #define REFLECTION_TESTREG reflection_high
  24 #endif
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 int get_fpga_state(unsigned dev)
  29 {
  30         return gd->arch.fpga_state[dev];
  31 }
  32
  33 int board_early_init_f(void)
  34 {
  35         unsigned k;
  36
  37         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  38                 gd->arch.fpga_state[k] = 0;
  39
  40         return 0;
  41 }
  42
  43 int board_early_init_r(void)
  44 {
  45         unsigned k;
  46         unsigned ctr;
  47
  48         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  49                 gd->arch.fpga_state[k] = 0;
  50
  51         /*
  52          * reset FPGA
  53          */
  54         mpc8308_init();
  55
  56         mpc8308_set_fpga_reset(1);
  57
  58         mpc8308_setup_hw();
  59
  60         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  61                 ctr = 0;
  62                 while (!mpc8308_get_fpga_done(k)) {
  63                         udelay(100000);
  64                         if (ctr++ > 5) {
  65                                 gd->arch.fpga_state[k] |=
  66                                         FPGA_STATE_DONE_FAILED;
  67                                 break;
  68                         }
  69                 }
  70         }
  71
  72         udelay(10);
  73
  74         mpc8308_set_fpga_reset(0);
  75
  76         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  77                 /*
  78                  * wait for fpga out of reset
  79                  */
  80                 ctr = 0;
  81                 while (1) {
  82                         u16 val;
  83
  84                         FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
  85
  86                         FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
  87                         if (val == REFLECTION_TESTPATTERN_INV)
  88                                 break;
  89
  90                         udelay(100000);
  91                         if (ctr++ > 5) {
  92                                 gd->arch.fpga_state[k] |=
  93                                         FPGA_STATE_REFLECTION_FAILED;
  94                                 break;
  95                         }
  96                 }
  97         }
  98
  99         return 0;
 100 }